Mailing List Archive

[PATCH][SVM] Update SVM V_TPR register on CR8 and MMIO accesses to APIC TPR
This patches ensures that the V_TPR stays in synch with the HVM VLAPIC
by reflecting writes to the TPR via MMIO and CR8 on to the VMCB's V_TPR
member. Although we currently set IGN_TPR to 1, this code makes sure
that the V_TPR is correct if we ever do otherwise.

If possible, please apply to xen-3.0.4-testing.

Signed-off-by: Travis Betak <travis.betak@amd.com>

--travis