Currently, RISC-V requires two extensions: _zbb and _zihintpause.
This patch introduces a compiler check to check if these extensions
are supported.
Additionally, it introduces the riscv/booting.txt file, which contains
information about the extensions that should be supported by the platform.
In the future, a feature will be introduced to check whether an extension
is supported at runtime.
However, this feature requires functionality for parsing device tree
source (DTS), which is not yet available.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes in V7:
- add variables for each extension separately.
- create variable for abi and compilation flags to not repeat the same in several
places.
- update architectures to use generic implementations
---
Changes in V6:
- new patch for this patch series
---
docs/misc/riscv/booting.txt | 16 ++++++++++++++++
xen/arch/riscv/arch.mk | 15 +++++++++++++--
2 files changed, 29 insertions(+), 2 deletions(-)
create mode 100644 docs/misc/riscv/booting.txt
diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt
new file mode 100644
index 0000000000..cb4d79f12c
--- /dev/null
+++ b/docs/misc/riscv/booting.txt
@@ -0,0 +1,16 @@
+System requirements
+===================
+
+The following extensions are expected to be supported by a system on which
+Xen is run:
+- Zbb:
+ RISC-V doesn't have a CLZ instruction in the base ISA.
+ As a consequence, __builtin_ffs() emits a library call to ffs() on GCC,
+ or a de Bruijn sequence on Clang.
+ Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits
+ a very simple sequence.
+ The similar issue occurs with other __builtin_<bitop>, so it is needed to
+ provide a generic version of bitops in RISC-V bitops.h
+- Zihintpause:
+ On a system that doesn't have this extension, cpu_relax() should be
+ implemented properly.
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 8403f96b6f..24a7461bcc 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -3,16 +3,27 @@
$(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS))
-CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64
+riscv-abi-$(CONFIG_RISCV_32) := -mabi=ilp32
+riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64
riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
+riscv-generic-flags := $(riscv-abi-y) -march=$(riscv-march-y)
+
+zbb := $(call as-insn,$(CC) $(riscv-generic-flags)_zbb,"",_zbb)
+zihintpause := $(call as-insn,\
+ $(CC) $(riscv-generic-flags)_zihintpause,"pause",_zihintpause)
+
+extensions := $(zbb) $(zihintpause)
+
+extensions := $(subst $(space),,$(extensions))
+
# Note that -mcmodel=medany is used so that Xen can be mapped
# into the upper half _or_ the lower half of the address space.
# -mcmodel=medlow would force Xen into the lower half.
-CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany
+CFLAGS += $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=medany
# TODO: Drop override when more of the build is working
override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o
--
2.43.0
This patch introduces a compiler check to check if these extensions
are supported.
Additionally, it introduces the riscv/booting.txt file, which contains
information about the extensions that should be supported by the platform.
In the future, a feature will be introduced to check whether an extension
is supported at runtime.
However, this feature requires functionality for parsing device tree
source (DTS), which is not yet available.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes in V7:
- add variables for each extension separately.
- create variable for abi and compilation flags to not repeat the same in several
places.
- update architectures to use generic implementations
---
Changes in V6:
- new patch for this patch series
---
docs/misc/riscv/booting.txt | 16 ++++++++++++++++
xen/arch/riscv/arch.mk | 15 +++++++++++++--
2 files changed, 29 insertions(+), 2 deletions(-)
create mode 100644 docs/misc/riscv/booting.txt
diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt
new file mode 100644
index 0000000000..cb4d79f12c
--- /dev/null
+++ b/docs/misc/riscv/booting.txt
@@ -0,0 +1,16 @@
+System requirements
+===================
+
+The following extensions are expected to be supported by a system on which
+Xen is run:
+- Zbb:
+ RISC-V doesn't have a CLZ instruction in the base ISA.
+ As a consequence, __builtin_ffs() emits a library call to ffs() on GCC,
+ or a de Bruijn sequence on Clang.
+ Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits
+ a very simple sequence.
+ The similar issue occurs with other __builtin_<bitop>, so it is needed to
+ provide a generic version of bitops in RISC-V bitops.h
+- Zihintpause:
+ On a system that doesn't have this extension, cpu_relax() should be
+ implemented properly.
diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 8403f96b6f..24a7461bcc 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -3,16 +3,27 @@
$(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS))
-CFLAGS-$(CONFIG_RISCV_64) += -mabi=lp64
+riscv-abi-$(CONFIG_RISCV_32) := -mabi=ilp32
+riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64
riscv-march-$(CONFIG_RISCV_ISA_RV64G) := rv64g
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
+riscv-generic-flags := $(riscv-abi-y) -march=$(riscv-march-y)
+
+zbb := $(call as-insn,$(CC) $(riscv-generic-flags)_zbb,"",_zbb)
+zihintpause := $(call as-insn,\
+ $(CC) $(riscv-generic-flags)_zihintpause,"pause",_zihintpause)
+
+extensions := $(zbb) $(zihintpause)
+
+extensions := $(subst $(space),,$(extensions))
+
# Note that -mcmodel=medany is used so that Xen can be mapped
# into the upper half _or_ the lower half of the address space.
# -mcmodel=medlow would force Xen into the lower half.
-CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany
+CFLAGS += $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=medany
# TODO: Drop override when more of the build is working
override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o
--
2.43.0