# HG changeset patch
# User Keir Fraser <keir@xen.org>
# Date 1301316248 -3600
# Node ID 9549c04a8384d18395bf036eeab0c6af2ff45aa2
# Parent bbf4b6dd9c3214637476972e96cd0d3cd9cb3844
x86: Remove _PAGE_NX defintiion (with implicit use of cpu_has_nx).
Most users can use _PAGE_NX_BIT directly.
The few genuine users in mm.c can do the cpu_has_nx check more clearly
in other ways.
Signed-off-by: Keir Fraser <keir@xen.org>
---
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/mm.c
--- a/xen/arch/x86/mm.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/mm.c Mon Mar 28 13:44:08 2011 +0100
@@ -161,6 +161,30 @@
#endif
static void put_superpage(unsigned long mfn);
+static uint32_t base_disallow_mask;
+#define L1_DISALLOW_MASK (base_disallow_mask | _PAGE_GNTTAB)
+#define L2_DISALLOW_MASK (base_disallow_mask & ~_PAGE_PSE)
+
+#if defined(__x86_64__)
+
+#define l3_disallow_mask(d) (!is_pv_32on64_domain(d) ? \
+ base_disallow_mask : \
+ 0xFFFFF198U)
+
+#define L4_DISALLOW_MASK (base_disallow_mask)
+
+#ifdef USER_MAPPINGS_ARE_GLOBAL
+/* Global bit is allowed to be set on L1 PTEs. Intended for user mappings. */
+#undef L1_DISALLOW_MASK
+#define L1_DISALLOW_MASK ((base_disallow_mask | _PAGE_GNTTAB) & ~_PAGE_GLOBAL)
+#endif
+
+#elif defined (__i386__)
+
+#define l3_disallow_mask(d) 0xFFFFF1FEU /* must-be-zero */
+
+#endif
+
#define l1_disallow_mask(d) \
((d != dom_io) && \
(rangeset_is_empty((d)->iomem_caps) && \
@@ -170,15 +194,6 @@
L1_DISALLOW_MASK : (L1_DISALLOW_MASK & ~PAGE_CACHE_ATTRS))
#ifdef __x86_64__
-l2_pgentry_t *compat_idle_pg_table_l2 = NULL;
-#define l3_disallow_mask(d) (!is_pv_32on64_domain(d) ? \
- L3_DISALLOW_MASK : \
- COMPAT_L3_DISALLOW_MASK)
-#else
-#define l3_disallow_mask(d) L3_DISALLOW_MASK
-#endif
-
-#ifdef __x86_64__
static void __init init_spagetable(void)
{
unsigned long s, start = SPAGETABLE_VIRT_START;
@@ -273,6 +288,16 @@
{
unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
+ /* Basic guest-accessible flags: PRESENT, R/W, USER, A/D, AVAIL[0,1,2] */
+ base_disallow_mask = ~(_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|
+ _PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_AVAIL);
+ /* Allow guest access to the NX flag if hardware supports it. */
+ if ( cpu_has_nx )
+ base_disallow_mask &= ~_PAGE_NX_BIT;
+ /* On x86/64, range [62:52] is available for guest software use. */
+ if ( CONFIG_PAGING_LEVELS == 4 )
+ base_disallow_mask &= ~get_pte_flags((intpte_t)0x7ff << 52);
+
/*
* Initialise our DOMID_XEN domain.
* Any Xen-heap pages that we will allow to be mapped will have
@@ -3982,11 +4007,17 @@
unsigned int flags, unsigned int cache_flags)
{
l1_pgentry_t pte;
+ uint32_t grant_pte_flags;
if ( paging_mode_external(current->domain) )
return create_grant_p2m_mapping(addr, frame, flags, cache_flags);
- pte = l1e_from_pfn(frame, GRANT_PTE_FLAGS);
+ grant_pte_flags =
+ _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_GNTTAB;
+ if ( cpu_has_nx )
+ grant_pte_flags |= _PAGE_NX_BIT;
+
+ pte = l1e_from_pfn(frame, grant_pte_flags);
if ( (flags & GNTMAP_application_map) )
l1e_add_flags(pte,_PAGE_USER);
if ( !(flags & GNTMAP_readonly) )
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/mm/shadow/multi.c
--- a/xen/arch/x86/mm/shadow/multi.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/mm/shadow/multi.c Mon Mar 28 13:44:08 2011 +0100
@@ -842,8 +842,8 @@
/* Given the flags of two entries, are the new flags a strict
* increase in rights over the old ones? */
{
- u32 of = old_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX);
- u32 nf = new_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX);
+ u32 of = old_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX_BIT);
+ u32 nf = new_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX_BIT);
/* Flip the NX bit, since it's the only one that decreases rights;
* we calculate as if it were an "X" bit. */
of ^= _PAGE_NX_BIT;
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/traps.c Mon Mar 28 13:44:08 2011 +0100
@@ -1129,7 +1129,7 @@
disallowed_flags = 0;
if ( error_code & PFEC_insn_fetch )
- disallowed_flags |= _PAGE_NX;
+ disallowed_flags |= _PAGE_NX_BIT;
mfn = cr3 >> PAGE_SHIFT;
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/x86_64/mm.c
--- a/xen/arch/x86/x86_64/mm.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/x86_64/mm.c Mon Mar 28 13:44:08 2011 +0100
@@ -69,6 +69,8 @@
l2_pgentry_t __attribute__ ((__section__ (".bss.page_aligned")))
l2_bootmap[L2_PAGETABLE_ENTRIES];
+l2_pgentry_t *compat_idle_pg_table_l2;
+
int __mfn_valid(unsigned long mfn)
{
return likely(mfn < max_page) &&
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/page.h
--- a/xen/include/asm-x86/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -342,9 +342,6 @@
#define __PAGE_HYPERVISOR_NOCACHE \
(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED)
-#define GRANT_PTE_FLAGS \
- (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NX | _PAGE_GNTTAB)
-
#ifndef __ASSEMBLY__
static inline int get_order_from_bytes(paddr_t size)
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/x86_32/page.h
--- a/xen/include/asm-x86/x86_32/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/x86_32/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -116,22 +116,12 @@
* 32-bit flags = (pte[63:44],pte[11:0])
*/
-#define _PAGE_NX_BIT (1U<<31)
-#define _PAGE_NX (cpu_has_nx ? _PAGE_NX_BIT : 0)
-
/* Extract flags into 32-bit integer, or turn 32-bit flags into a pte mask. */
#define get_pte_flags(x) (((int)((x) >> 32) & ~0xFFF) | ((int)(x) & 0xFFF))
#define put_pte_flags(x) (((intpte_t)((x) & ~0xFFF) << 32) | ((x) & 0xFFF))
-/*
- * Disallow unused flag bits plus PAT/PSE, PCD, PWT and GLOBAL.
- * Permit the NX bit if the hardware supports it.
- */
-#define BASE_DISALLOW_MASK (0xFFFFF198U & ~_PAGE_NX)
-
-#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
-#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK & ~_PAGE_PSE)
-#define L3_DISALLOW_MASK 0xFFFFF1FEU /* must-be-zero */
+/* Bit 31 of a 32-bit flag mask. This corresponds to bit 63 of a pte.*/
+#define _PAGE_NX_BIT (1U<<31)
#endif /* __X86_32_PAGE_H__ */
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/x86_64/page.h
--- a/xen/include/asm-x86/x86_64/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/x86_64/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -154,25 +154,10 @@
/* Bit 23 of a 24-bit flag mask. This corresponds to bit 63 of a pte.*/
#define _PAGE_NX_BIT (1U<<23)
-#define _PAGE_NX (cpu_has_nx ? _PAGE_NX_BIT : 0U)
/* Bit 22 of a 24-bit flag mask. This corresponds to bit 62 of a pte.*/
#define _PAGE_GNTTAB (1U<<22)
-/*
- * Disallow unused flag bits plus PAT/PSE, PCD, PWT and GLOBAL.
- * Permit the NX bit if the hardware supports it.
- * Note that range [62:52] is available for software use on x86/64.
- */
-#define BASE_DISALLOW_MASK (0xFF800198U & ~_PAGE_NX)
-
-#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
-#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK & ~_PAGE_PSE)
-#define L3_DISALLOW_MASK (BASE_DISALLOW_MASK)
-#define L4_DISALLOW_MASK (BASE_DISALLOW_MASK)
-
-#define COMPAT_L3_DISALLOW_MASK 0xFFFFF198U
-
#define PAGE_HYPERVISOR (__PAGE_HYPERVISOR | _PAGE_GLOBAL)
#define PAGE_HYPERVISOR_NOCACHE (__PAGE_HYPERVISOR_NOCACHE | _PAGE_GLOBAL)
@@ -184,9 +169,6 @@
* is asserted for both.
*/
#define _PAGE_GUEST_KERNEL (1U<<12)
-/* Global bit is allowed to be set on L1 PTEs. Intended for user mappings. */
-#undef L1_DISALLOW_MASK
-#define L1_DISALLOW_MASK ((BASE_DISALLOW_MASK | _PAGE_GNTTAB) & ~_PAGE_GLOBAL)
#else
#define _PAGE_GUEST_KERNEL 0
#endif
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# User Keir Fraser <keir@xen.org>
# Date 1301316248 -3600
# Node ID 9549c04a8384d18395bf036eeab0c6af2ff45aa2
# Parent bbf4b6dd9c3214637476972e96cd0d3cd9cb3844
x86: Remove _PAGE_NX defintiion (with implicit use of cpu_has_nx).
Most users can use _PAGE_NX_BIT directly.
The few genuine users in mm.c can do the cpu_has_nx check more clearly
in other ways.
Signed-off-by: Keir Fraser <keir@xen.org>
---
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/mm.c
--- a/xen/arch/x86/mm.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/mm.c Mon Mar 28 13:44:08 2011 +0100
@@ -161,6 +161,30 @@
#endif
static void put_superpage(unsigned long mfn);
+static uint32_t base_disallow_mask;
+#define L1_DISALLOW_MASK (base_disallow_mask | _PAGE_GNTTAB)
+#define L2_DISALLOW_MASK (base_disallow_mask & ~_PAGE_PSE)
+
+#if defined(__x86_64__)
+
+#define l3_disallow_mask(d) (!is_pv_32on64_domain(d) ? \
+ base_disallow_mask : \
+ 0xFFFFF198U)
+
+#define L4_DISALLOW_MASK (base_disallow_mask)
+
+#ifdef USER_MAPPINGS_ARE_GLOBAL
+/* Global bit is allowed to be set on L1 PTEs. Intended for user mappings. */
+#undef L1_DISALLOW_MASK
+#define L1_DISALLOW_MASK ((base_disallow_mask | _PAGE_GNTTAB) & ~_PAGE_GLOBAL)
+#endif
+
+#elif defined (__i386__)
+
+#define l3_disallow_mask(d) 0xFFFFF1FEU /* must-be-zero */
+
+#endif
+
#define l1_disallow_mask(d) \
((d != dom_io) && \
(rangeset_is_empty((d)->iomem_caps) && \
@@ -170,15 +194,6 @@
L1_DISALLOW_MASK : (L1_DISALLOW_MASK & ~PAGE_CACHE_ATTRS))
#ifdef __x86_64__
-l2_pgentry_t *compat_idle_pg_table_l2 = NULL;
-#define l3_disallow_mask(d) (!is_pv_32on64_domain(d) ? \
- L3_DISALLOW_MASK : \
- COMPAT_L3_DISALLOW_MASK)
-#else
-#define l3_disallow_mask(d) L3_DISALLOW_MASK
-#endif
-
-#ifdef __x86_64__
static void __init init_spagetable(void)
{
unsigned long s, start = SPAGETABLE_VIRT_START;
@@ -273,6 +288,16 @@
{
unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
+ /* Basic guest-accessible flags: PRESENT, R/W, USER, A/D, AVAIL[0,1,2] */
+ base_disallow_mask = ~(_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|
+ _PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_AVAIL);
+ /* Allow guest access to the NX flag if hardware supports it. */
+ if ( cpu_has_nx )
+ base_disallow_mask &= ~_PAGE_NX_BIT;
+ /* On x86/64, range [62:52] is available for guest software use. */
+ if ( CONFIG_PAGING_LEVELS == 4 )
+ base_disallow_mask &= ~get_pte_flags((intpte_t)0x7ff << 52);
+
/*
* Initialise our DOMID_XEN domain.
* Any Xen-heap pages that we will allow to be mapped will have
@@ -3982,11 +4007,17 @@
unsigned int flags, unsigned int cache_flags)
{
l1_pgentry_t pte;
+ uint32_t grant_pte_flags;
if ( paging_mode_external(current->domain) )
return create_grant_p2m_mapping(addr, frame, flags, cache_flags);
- pte = l1e_from_pfn(frame, GRANT_PTE_FLAGS);
+ grant_pte_flags =
+ _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_GNTTAB;
+ if ( cpu_has_nx )
+ grant_pte_flags |= _PAGE_NX_BIT;
+
+ pte = l1e_from_pfn(frame, grant_pte_flags);
if ( (flags & GNTMAP_application_map) )
l1e_add_flags(pte,_PAGE_USER);
if ( !(flags & GNTMAP_readonly) )
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/mm/shadow/multi.c
--- a/xen/arch/x86/mm/shadow/multi.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/mm/shadow/multi.c Mon Mar 28 13:44:08 2011 +0100
@@ -842,8 +842,8 @@
/* Given the flags of two entries, are the new flags a strict
* increase in rights over the old ones? */
{
- u32 of = old_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX);
- u32 nf = new_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX);
+ u32 of = old_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX_BIT);
+ u32 nf = new_flags & (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_NX_BIT);
/* Flip the NX bit, since it's the only one that decreases rights;
* we calculate as if it were an "X" bit. */
of ^= _PAGE_NX_BIT;
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/traps.c Mon Mar 28 13:44:08 2011 +0100
@@ -1129,7 +1129,7 @@
disallowed_flags = 0;
if ( error_code & PFEC_insn_fetch )
- disallowed_flags |= _PAGE_NX;
+ disallowed_flags |= _PAGE_NX_BIT;
mfn = cr3 >> PAGE_SHIFT;
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/arch/x86/x86_64/mm.c
--- a/xen/arch/x86/x86_64/mm.c Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/arch/x86/x86_64/mm.c Mon Mar 28 13:44:08 2011 +0100
@@ -69,6 +69,8 @@
l2_pgentry_t __attribute__ ((__section__ (".bss.page_aligned")))
l2_bootmap[L2_PAGETABLE_ENTRIES];
+l2_pgentry_t *compat_idle_pg_table_l2;
+
int __mfn_valid(unsigned long mfn)
{
return likely(mfn < max_page) &&
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/page.h
--- a/xen/include/asm-x86/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -342,9 +342,6 @@
#define __PAGE_HYPERVISOR_NOCACHE \
(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED)
-#define GRANT_PTE_FLAGS \
- (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NX | _PAGE_GNTTAB)
-
#ifndef __ASSEMBLY__
static inline int get_order_from_bytes(paddr_t size)
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/x86_32/page.h
--- a/xen/include/asm-x86/x86_32/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/x86_32/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -116,22 +116,12 @@
* 32-bit flags = (pte[63:44],pte[11:0])
*/
-#define _PAGE_NX_BIT (1U<<31)
-#define _PAGE_NX (cpu_has_nx ? _PAGE_NX_BIT : 0)
-
/* Extract flags into 32-bit integer, or turn 32-bit flags into a pte mask. */
#define get_pte_flags(x) (((int)((x) >> 32) & ~0xFFF) | ((int)(x) & 0xFFF))
#define put_pte_flags(x) (((intpte_t)((x) & ~0xFFF) << 32) | ((x) & 0xFFF))
-/*
- * Disallow unused flag bits plus PAT/PSE, PCD, PWT and GLOBAL.
- * Permit the NX bit if the hardware supports it.
- */
-#define BASE_DISALLOW_MASK (0xFFFFF198U & ~_PAGE_NX)
-
-#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
-#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK & ~_PAGE_PSE)
-#define L3_DISALLOW_MASK 0xFFFFF1FEU /* must-be-zero */
+/* Bit 31 of a 32-bit flag mask. This corresponds to bit 63 of a pte.*/
+#define _PAGE_NX_BIT (1U<<31)
#endif /* __X86_32_PAGE_H__ */
diff -r bbf4b6dd9c32 -r 9549c04a8384 xen/include/asm-x86/x86_64/page.h
--- a/xen/include/asm-x86/x86_64/page.h Mon Mar 28 12:07:52 2011 +0100
+++ b/xen/include/asm-x86/x86_64/page.h Mon Mar 28 13:44:08 2011 +0100
@@ -154,25 +154,10 @@
/* Bit 23 of a 24-bit flag mask. This corresponds to bit 63 of a pte.*/
#define _PAGE_NX_BIT (1U<<23)
-#define _PAGE_NX (cpu_has_nx ? _PAGE_NX_BIT : 0U)
/* Bit 22 of a 24-bit flag mask. This corresponds to bit 62 of a pte.*/
#define _PAGE_GNTTAB (1U<<22)
-/*
- * Disallow unused flag bits plus PAT/PSE, PCD, PWT and GLOBAL.
- * Permit the NX bit if the hardware supports it.
- * Note that range [62:52] is available for software use on x86/64.
- */
-#define BASE_DISALLOW_MASK (0xFF800198U & ~_PAGE_NX)
-
-#define L1_DISALLOW_MASK (BASE_DISALLOW_MASK | _PAGE_GNTTAB)
-#define L2_DISALLOW_MASK (BASE_DISALLOW_MASK & ~_PAGE_PSE)
-#define L3_DISALLOW_MASK (BASE_DISALLOW_MASK)
-#define L4_DISALLOW_MASK (BASE_DISALLOW_MASK)
-
-#define COMPAT_L3_DISALLOW_MASK 0xFFFFF198U
-
#define PAGE_HYPERVISOR (__PAGE_HYPERVISOR | _PAGE_GLOBAL)
#define PAGE_HYPERVISOR_NOCACHE (__PAGE_HYPERVISOR_NOCACHE | _PAGE_GLOBAL)
@@ -184,9 +169,6 @@
* is asserted for both.
*/
#define _PAGE_GUEST_KERNEL (1U<<12)
-/* Global bit is allowed to be set on L1 PTEs. Intended for user mappings. */
-#undef L1_DISALLOW_MASK
-#define L1_DISALLOW_MASK ((BASE_DISALLOW_MASK | _PAGE_GNTTAB) & ~_PAGE_GLOBAL)
#else
#define _PAGE_GUEST_KERNEL 0
#endif
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