Mailing List Archive

[xen-unstable] x86: add explicit size suffixes to some assembly instructions.
# HG changeset patch
# User Tim Deegan <Tim.Deegan@citrix.com>
# Date 1299496871 0
# Node ID 5317eb6567616c5adb1b0e3c4c2a001eb38bc7a5
# Parent 5f68924489f569539fc60e46f866bd75ecc82134
x86: add explicit size suffixes to some assembly instructions.
This is needed to compile xen with clang.

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
---


diff -r 5f68924489f5 -r 5317eb656761 xen/arch/x86/acpi/suspend.c
--- a/xen/arch/x86/acpi/suspend.c Mon Mar 07 11:21:11 2011 +0000
+++ b/xen/arch/x86/acpi/suspend.c Mon Mar 07 11:21:11 2011 +0000
@@ -28,7 +28,7 @@

#if defined(CONFIG_X86_64)
asm volatile (
- "mov %%ds,(%0); mov %%es,2(%0); mov %%fs,4(%0); mov %%gs,6(%0)"
+ "movw %%ds,(%0); movw %%es,2(%0); movw %%fs,4(%0); movw %%gs,6(%0)"
: : "r" (saved_segs) : "memory" );
rdmsrl(MSR_FS_BASE, saved_fs_base);
rdmsrl(MSR_GS_BASE, saved_gs_base);
@@ -75,7 +75,7 @@
if ( !is_idle_vcpu(curr) )
{
asm volatile (
- "mov (%0),%%ds; mov 2(%0),%%es; mov 4(%0),%%fs"
+ "movw (%0),%%ds; movw 2(%0),%%es; movw 4(%0),%%fs"
: : "r" (saved_segs) : "memory" );
do_set_segment_base(SEGBASE_GS_USER_SEL, saved_segs[3]);
}
diff -r 5f68924489f5 -r 5317eb656761 xen/arch/x86/x86_emulate/x86_emulate.c
--- a/xen/arch/x86/x86_emulate/x86_emulate.c Mon Mar 07 11:21:11 2011 +0000
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c Mon Mar 07 11:21:11 2011 +0000
@@ -2678,7 +2678,7 @@
emulate_fpu_insn_memsrc("fiaddl", src.val);
break;
case 1: /* fimul m64i */
- emulate_fpu_insn_memsrc("fimul", src.val);
+ emulate_fpu_insn_memsrc("fimuls", src.val);
break;
case 2: /* ficom m64i */
emulate_fpu_insn_memsrc("ficoml", src.val);
@@ -2897,28 +2897,28 @@
switch ( modrm_reg & 7 )
{
case 0: /* fiadd m16i */
- emulate_fpu_insn_memsrc("fiadd", src.val);
+ emulate_fpu_insn_memsrc("fiadds", src.val);
break;
case 1: /* fimul m16i */
- emulate_fpu_insn_memsrc("fimul", src.val);
+ emulate_fpu_insn_memsrc("fimuls", src.val);
break;
case 2: /* ficom m16i */
- emulate_fpu_insn_memsrc("ficom", src.val);
+ emulate_fpu_insn_memsrc("ficoms", src.val);
break;
case 3: /* ficomp m16i */
- emulate_fpu_insn_memsrc("ficomp", src.val);
+ emulate_fpu_insn_memsrc("ficomps", src.val);
break;
case 4: /* fisub m16i */
- emulate_fpu_insn_memsrc("fisub", src.val);
+ emulate_fpu_insn_memsrc("fisubs", src.val);
break;
case 5: /* fisubr m16i */
- emulate_fpu_insn_memsrc("fisubr", src.val);
+ emulate_fpu_insn_memsrc("fisubrs", src.val);
break;
case 6: /* fidiv m16i */
- emulate_fpu_insn_memsrc("fidiv", src.val);
+ emulate_fpu_insn_memsrc("fidivs", src.val);
break;
case 7: /* fidivr m16i */
- emulate_fpu_insn_memsrc("fidivr", src.val);
+ emulate_fpu_insn_memsrc("fidivrs", src.val);
break;
default:
goto cannot_emulate;
@@ -2950,25 +2950,25 @@
if ( (rc = ops->read(src.mem.seg, src.mem.off, &src.val,
src.bytes, ctxt)) != 0 )
goto done;
- emulate_fpu_insn_memsrc("fild", src.val);
+ emulate_fpu_insn_memsrc("filds", src.val);
break;
case 1: /* fisttp m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fisttp", dst.val);
+ emulate_fpu_insn_memdst("fisttps", dst.val);
break;
case 2: /* fist m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fist", dst.val);
+ emulate_fpu_insn_memdst("fists", dst.val);
break;
case 3: /* fistp m16i */
ea.bytes = 2;
dst = ea;
dst.type = OP_MEM;
- emulate_fpu_insn_memdst("fistp", dst.val);
+ emulate_fpu_insn_memdst("fistps", dst.val);
break;
case 4: /* fbld m80dec */
ea.bytes = 10;

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