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# HG changeset patch
# User Keir Fraser <keir@xen.org>
# Date 1296145047 0
# Node ID 6067a17114bcc64adb3b04dfaac52f2d660867d9
# Parent 3b00ee057c4ac8f404a516f89b1497570f8e5e5f
hvm: allow pass-through of new FPU/ALU CPUID features

there are some new CPUID features that are safe for guests to see, as
they don't require OS awareness (FPU/ALU related instructions only).
Among features for new AMD CPUs there is also the PCLMULQDQ bit, which
Intel CPU have already for quite a while.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
tools/libxc/xc_cpufeature.h | 2 ++
tools/libxc/xc_cpuid_x86.c | 7 ++++++-
tools/libxl/libxl_cpuid.c | 1 +
xen/include/asm-x86/cpufeature.h | 2 ++
4 files changed, 11 insertions(+), 1 deletion(-)

diff -r 3b00ee057c4a -r 6067a17114bc tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Jan 27 16:12:07 2011 +0000
+++ b/tools/libxc/xc_cpufeature.h Thu Jan 27 16:17:27 2011 +0000
@@ -83,6 +83,7 @@

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less multiplication */
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
@@ -104,6 +105,7 @@
#define X86_FEATURE_AES (4*32+25) /* AES acceleration instructions */
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C (4*32+29) /* Half-precision convert instruction */
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
diff -r 3b00ee057c4a -r 6067a17114bc tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Jan 27 16:12:07 2011 +0000
+++ b/tools/libxc/xc_cpuid_x86.c Thu Jan 27 16:17:27 2011 +0000
@@ -101,7 +101,10 @@ static void amd_xc_cpuid_policy(
bitmaskof(X86_FEATURE_ABM) |
bitmaskof(X86_FEATURE_SSE4A) |
bitmaskof(X86_FEATURE_MISALIGNSSE) |
- bitmaskof(X86_FEATURE_3DNOWPREFETCH));
+ bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
+ bitmaskof(X86_FEATURE_XOP) |
+ bitmaskof(X86_FEATURE_FMA4) |
+ bitmaskof(X86_FEATURE_TBM));
regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
(is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
@@ -251,12 +254,14 @@ static void xc_cpuid_hvm_policy(
regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1);

regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
+ bitmaskof(X86_FEATURE_PCLMULQDQ) |
bitmaskof(X86_FEATURE_SSSE3) |
bitmaskof(X86_FEATURE_CX16) |
bitmaskof(X86_FEATURE_SSE4_1) |
bitmaskof(X86_FEATURE_SSE4_2) |
bitmaskof(X86_FEATURE_POPCNT) |
bitmaskof(X86_FEATURE_AES) |
+ bitmaskof(X86_FEATURE_F16C) |
((xfeature_mask != 0) ?
(bitmaskof(X86_FEATURE_AVX) |
bitmaskof(X86_FEATURE_XSAVE)) : 0));
diff -r 3b00ee057c4a -r 6067a17114bc tools/libxl/libxl_cpuid.c
--- a/tools/libxl/libxl_cpuid.c Thu Jan 27 16:12:07 2011 +0000
+++ b/tools/libxl/libxl_cpuid.c Thu Jan 27 16:17:27 2011 +0000
@@ -115,6 +115,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"dscpl", 0x00000001, NA, CPUID_REG_ECX, 4, 1},
{"monitor", 0x00000001, NA, CPUID_REG_ECX, 3, 1},
{"dtes64", 0x00000001, NA, CPUID_REG_ECX, 2, 1},
+ {"pclmulqdq", 0x00000001, NA, CPUID_REG_ECX, 1, 1},
{"sse3", 0x00000001, NA, CPUID_REG_ECX, 0, 1},
{"pbe", 0x00000001, NA, CPUID_REG_EDX, 31, 1},
{"ia64", 0x00000001, NA, CPUID_REG_EDX, 30, 1},
diff -r 3b00ee057c4a -r 6067a17114bc xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Thu Jan 27 16:12:07 2011 +0000
+++ b/xen/include/asm-x86/cpufeature.h Thu Jan 27 16:17:27 2011 +0000
@@ -82,6 +82,7 @@

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
@@ -103,6 +104,7 @@
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
#define X86_FEATURE_OSXSAVE (4*32+27) /* OSXSAVE */
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C (4*32+29) /* Half-precision convert instruction */
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

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