Mailing List Archive

# HG changeset patch
# User Alex Williamson <alex.williamson@hp.com>
# Date 1187278674 21600
# Node ID f317c27973f51f797677edecdbc1c99aed81f428
# Parent cd51fa91956be20dbd744d46117f7f989e08c334
[IA64] Shrink vtlb size

Instrumenting thash_purge_all() shows a very low usage of vtlb
entries (21 at most).

This patch shrinks the default vtlb size from 512KB to 16KB
to optimize memory. This also speeds up ptc_e emulation.
To improve the hash function, frequency of collision never changed
and there is no performance degradation.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
---
xen/arch/ia64/vmx/vmmu.c | 40 ++++------------------------------------
xen/arch/ia64/vmx/vtlb.c | 17 ++++++++++++++---
xen/include/asm-ia64/vmmu.h | 2 +-
3 files changed, 19 insertions(+), 40 deletions(-)

diff -r cd51fa91956b -r f317c27973f5 xen/arch/ia64/vmx/vmmu.c
--- a/xen/arch/ia64/vmx/vmmu.c Sun Aug 12 14:50:02 2007 -0600
+++ b/xen/arch/ia64/vmx/vmmu.c Thu Aug 16 09:37:54 2007 -0600
@@ -32,9 +32,9 @@ static void __init parse_vtlb_size(char

if (sz > 0) {
default_vtlb_sz = fls(sz - 1);
- /* minimum 256KB (since calculated tag might be broken) */
- if (default_vtlb_sz < 18)
- default_vtlb_sz = 18;
+ /* minimum 16KB (for tag uniqueness) */
+ if (default_vtlb_sz < 14)
+ default_vtlb_sz = 14;
}
}

@@ -240,40 +240,8 @@ void machine_tlb_insert(struct vcpu *v,
*/
void machine_tlb_purge(u64 va, u64 ps)
{
-// u64 psr;
-// psr = ia64_clear_ic();
ia64_ptcl(va, ps << 2);
-// ia64_set_psr(psr);
-// ia64_srlz_i();
-// return;
-}
-/*
-u64 machine_thash(u64 va)
-{
- return ia64_thash(va);
-}
-
-u64 machine_ttag(u64 va)
-{
- return ia64_ttag(va);
-}
-*/
-thash_data_t * vsa_thash(PTA vpta, u64 va, u64 vrr, u64 *tag)
-{
- u64 index,pfn,rid,pfn_bits;
- pfn_bits = vpta.size-5-8;
- pfn = REGION_OFFSET(va)>>_REGION_PAGE_SIZE(vrr);
- rid = _REGION_ID(vrr);
- index = ((rid&0xff)<<pfn_bits)|(pfn&((1UL<<pfn_bits)-1));
- *tag = ((rid>>8)&0xffff) | ((pfn >>pfn_bits)<<16);
- return (thash_data_t *)((vpta.base<<PTA_BASE_SHIFT)+(index<<5));
-// return ia64_call_vsa(PAL_VPS_THASH,va,vrr,vpta,0,0,0,0);
-}
-
-//u64 vsa_ttag(u64 va, u64 vrr)
-//{
-// return ia64_call_vsa(PAL_VPS_TTAG,va,vrr,0,0,0,0,0);
-//}
+}

int vhpt_enabled(VCPU *vcpu, uint64_t vadr, vhpt_ref_t ref)
{
diff -r cd51fa91956b -r f317c27973f5 xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c Sun Aug 12 14:50:02 2007 -0600
+++ b/xen/arch/ia64/vmx/vtlb.c Thu Aug 16 09:37:54 2007 -0600
@@ -286,6 +286,17 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
return ret;
}

+static thash_data_t * vtlb_thash(PTA vpta, u64 va, u64 vrr, u64 *tag)
+{
+ u64 index, pfn, rid;
+
+ pfn = REGION_OFFSET(va) >> _REGION_PAGE_SIZE(vrr);
+ rid = _REGION_ID(vrr);
+ index = (pfn ^ rid) & ((1UL << (vpta.size - 5)) - 1);
+ *tag = pfn ^ (rid << 39);
+ return (thash_data_t *)((vpta.base << PTA_BASE_SHIFT) + (index << 5));
+}
+
/*
* purge software guest tlb
*/
@@ -308,7 +319,7 @@ static void vtlb_purge(VCPU *v, u64 va,
size = PSIZE(rr_ps);
vrr.ps = rr_ps;
while (num) {
- cur = vsa_thash(hcb->pta, curadr, vrr.rrval, &tag);
+ cur = vtlb_thash(hcb->pta, curadr, vrr.rrval, &tag);
while (cur) {
if (cur->etag == tag && cur->ps == rr_ps)
cur->etag = 1UL << 63;
@@ -401,7 +412,7 @@ void vtlb_insert(VCPU *v, u64 pte, u64 i
vcpu_get_rr(v, va, &vrr.rrval);
vrr.ps = itir_ps(itir);
VMX(v, psbits[va >> 61]) |= (1UL << vrr.ps);
- hash_table = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
+ hash_table = vtlb_thash(hcb->pta, va, vrr.rrval, &tag);
cch = hash_table;
while (cch) {
if (INVALID_TLB(cch)) {
@@ -639,7 +650,7 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
ps = __ffs(psbits);
psbits &= ~(1UL << ps);
vrr.ps = ps;
- cch = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
+ cch = vtlb_thash(hcb->pta, va, vrr.rrval, &tag);
do {
if (cch->etag == tag && cch->ps == ps)
return cch;
diff -r cd51fa91956b -r f317c27973f5 xen/include/asm-ia64/vmmu.h
--- a/xen/include/asm-ia64/vmmu.h Sun Aug 12 14:50:02 2007 -0600
+++ b/xen/include/asm-ia64/vmmu.h Thu Aug 16 09:37:54 2007 -0600
@@ -24,7 +24,7 @@
#define XEN_TLBthash_H

#define MAX_CCN_DEPTH (15) // collision chain depth
-#define DEFAULT_VTLB_SZ (19) // 512K hash + 512K c-chain for VTLB
+#define DEFAULT_VTLB_SZ (14) // 16K hash + 16K c-chain for VTLB
#define DEFAULT_VHPT_SZ (23) // 8M hash + 8M c-chain for VHPT
#define VTLB(v,_x) (v->arch.vtlb._x)
#define VHPT(v,_x) (v->arch.vhpt._x)

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