Mailing List Archive

# HG changeset patch
# User Alex Williamson <alex.williamson@hp.com>
# Date 1186942402 21600
# Node ID 54c721bb6d452d8eb97a151c847c9276868ae5c5
# Parent 82f5fbe59e264465397d757b70874f45dd8c2b6c
[IA64] Minimal long vhpt format support

Signed-off-by: Juergen Gross juergen.gross@fujitsu-siemens.com
---
xen/arch/ia64/xen/hyperprivop.S | 10 +++++-----
xen/arch/ia64/xen/vcpu.c | 16 +++++++---------
2 files changed, 12 insertions(+), 14 deletions(-)

diff -r 82f5fbe59e26 -r 54c721bb6d45 xen/arch/ia64/xen/hyperprivop.S
--- a/xen/arch/ia64/xen/hyperprivop.S Sun Aug 12 12:06:43 2007 -0600
+++ b/xen/arch/ia64/xen/hyperprivop.S Sun Aug 12 12:13:22 2007 -0600
@@ -844,19 +844,19 @@ fast_tlb_no_tr_match:

1: // check the guest VHPT
adds r19 = XSI_PTA_OFS-XSI_PSR_IC_OFS, r18;;
- ld8 r19=[r19];;
- tbit.nz p7,p0=r19,IA64_PTA_VF_BIT;; // long format VHPT
-(p7) br.cond.spnt.few page_fault;;
+ ld8 r19=[r19]
// if (!rr.ve || !(pta & IA64_PTA_VE)) take slow way for now
// FIXME: later, we deliver an alt_d/i vector after thash and itir
- tbit.z p7,p0=r19,IA64_PTA_VE_BIT
-(p7) br.cond.spnt.few page_fault;;
extr.u r25=r17,61,3
adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
shl r25=r25,3;;
add r21=r21,r25;;
ld8 r22=[r21];;
tbit.z p7,p0=r22,0
+(p7) br.cond.spnt.few page_fault;;
+ tbit.z p7,p0=r19,IA64_PTA_VE_BIT
+(p7) br.cond.spnt.few page_fault;;
+ tbit.nz p7,p0=r19,IA64_PTA_VF_BIT // long format VHPT
(p7) br.cond.spnt.few page_fault;;

// compute and save away itir (r22 & RR_PS_MASK)
diff -r 82f5fbe59e26 -r 54c721bb6d45 xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c Sun Aug 12 12:06:43 2007 -0600
+++ b/xen/arch/ia64/xen/vcpu.c Sun Aug 12 12:13:22 2007 -0600
@@ -49,7 +49,6 @@ typedef union {
#define IA64_PTA_SZ_BIT 2
#define IA64_PTA_VF_BIT 8
#define IA64_PTA_BASE_BIT 15
-#define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
#define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)

#define IA64_PSR_NON_VIRT_BITS \
@@ -755,10 +754,6 @@ IA64FAULT vcpu_set_iva(VCPU * vcpu, u64

IA64FAULT vcpu_set_pta(VCPU * vcpu, u64 val)
{
- if (val & IA64_PTA_LFMT) {
- printk("*** No support for VHPT long format yet!!\n");
- return IA64_ILLOP_FAULT;
- }
if (val & (0x3f << 9)) /* reserved fields */
return IA64_RSVDREG_FAULT;
if (val & 2) /* reserved fields */
@@ -1753,10 +1748,6 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6

/* check guest VHPT */
pta = PSCB(vcpu, pta);
- if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
- panic_domain(vcpu_regs(vcpu), "can't do long format VHPT\n");
- //return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
- }

*itir = rr & (RR_RID_MASK | RR_PS_MASK);
// note: architecturally, iha is optionally set for alt faults but
@@ -1778,6 +1769,13 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6
IA64_ALT_INST_TLB_VECTOR;
}

+ if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
+ /*
+ * minimal support: vhpt walker is really dumb and won't find
+ * anything
+ */
+ return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
+ }
/* avoid recursively walking (short format) VHPT */
if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;

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