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Wrong cache size reported on Q6600
kernel at kolivas
Jun 28, 2007, 4:31 PM
Post #1 of 5 (697 views)
Permalink
This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
half's effective L2, I think it should be reporting 8192 instead of 4096.

On 2.6.22-rc6:

cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 0
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4806.38
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:

processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.73
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:

processor : 2
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 2
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.86
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:

processor : 3
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
stepping : 7
cpu MHz : 2401.919
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 3
cpu cores : 4
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 4803.93
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:

--
-ck
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Re: Wrong cache size reported on Q6600 [ In reply to ]
kyle at mcmartin
Jun 28, 2007, 4:25 PM
Post #2 of 5 (673 views)
Permalink
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.
>

Each pair of cores appears to get 4MB of L2, according to the product
brief PDF on Intel's website.

Cheers, Kyle
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Re: Wrong cache size reported on Q6600 [ In reply to ]
suresh.b.siddha at intel
Jun 28, 2007, 4:33 PM
Post #3 of 5 (680 views)
Permalink
On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> half's effective L2, I think it should be reporting 8192 instead of 4096.

There are two L2's, each of 4MB. Each L2 shared by two cores.

thanks,
suresh

>
> On 2.6.22-rc6:
>
> cat /proc/cpuinfo
> processor : 0
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 0
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4806.38
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 1
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 1
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.73
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 2
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 2
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.86
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> processor : 3
> vendor_id : GenuineIntel
> cpu family : 6
> model : 15
> model name : Intel(R) Core(TM)2 Quad CPU @ 2.40GHz
> stepping : 7
> cpu MHz : 2401.919
> cache size : 4096 KB
> physical id : 0
> siblings : 4
> core id : 3
> cpu cores : 4
> fpu : yes
> fpu_exception : yes
> cpuid level : 10
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
> cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm
> constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
> bogomips : 4803.93
> clflush size : 64
> cache_alignment : 64
> address sizes : 36 bits physical, 48 bits virtual
> power management:
>
> --
> -ck
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Re: Wrong cache size reported on Q6600 [ In reply to ]
kernel at kolivas
Jun 28, 2007, 4:57 PM
Post #4 of 5 (677 views)
Permalink
On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
> > This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
> > half's effective L2, I think it should be reporting 8192 instead of 4096.
>
> There are two L2's, each of 4MB. Each L2 shared by two cores.

That was what I wasn't sure of as I said above; thanks for clarifying.

--
-ck
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Re: Wrong cache size reported on Q6600 [ In reply to ]
cebbert at redhat
Jun 29, 2007, 8:31 AM
Post #5 of 5 (668 views)
Permalink
On 06/28/2007 07:57 PM, Con Kolivas wrote:
> On Friday 29 June 2007 09:33, Siddha, Suresh B wrote:
>> On Fri, Jun 29, 2007 at 09:31:44AM +1000, Con Kolivas wrote:
>>> This is a Q6600 which has cache size of 8 MB. Unless it's reporting each
>>> half's effective L2, I think it should be reporting 8192 instead of 4096.
>> There are two L2's, each of 4MB. Each L2 shared by two cores.
>
> That was what I wasn't sure of as I said above; thanks for clarifying.
>

You really need to look in /sys/devices/system/cpu/cpuX/cache/ to get
any kind of useful information.

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