Mailing List Archive: [PATCH 4/4] sound: jz4740: Enable codec clock during dai

[PATCH 4/4] sound: jz4740: Enable codec clock during dai_probe

Jan 26, 2015, 2:18 AM

Post #1 of 4 (47 views)

As we are moving away from platform to DT, we cant rely on the board
file to do this now. So enable it here.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
---
sound/soc/jz4740/jz4740-i2s.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
index 3c309fc..a7e4a7b 100644
--- a/sound/soc/jz4740/jz4740-i2s.c
+++ b/sound/soc/jz4740/jz4740-i2s.c
@@ -376,6 +376,10 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
JZ_AIC_CONF_I2S |
JZ_AIC_CONF_INTERNAL_CODEC;

+ /* enable codec sysclk */
+ clk_set_rate(i2s->clk_i2s, 12000000);
+ clk_prepare_enable(i2s->clk_i2s);
+
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);

--
1.9.1

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Re: [PATCH 4/4] sound: jz4740: Enable codec clock during dai_probe [ In reply to ]

lars at metafoo

Jan 26, 2015, 2:40 AM

Post #2 of 4 (45 views)

Permalink

On 01/26/2015 11:18 AM, Zubair Lutfullah Kakakhel wrote:
> As we are moving away from platform to DT, we cant rely on the board
> file to do this now. So enable it here.

I don't understand this changelog. The board file never did this. The driver
enables the clock in the startup() callback.

>
> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
> ---
> sound/soc/jz4740/jz4740-i2s.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
> index 3c309fc..a7e4a7b 100644
> --- a/sound/soc/jz4740/jz4740-i2s.c
> +++ b/sound/soc/jz4740/jz4740-i2s.c
> @@ -376,6 +376,10 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
> JZ_AIC_CONF_I2S |
> JZ_AIC_CONF_INTERNAL_CODEC;
>
> + /* enable codec sysclk */
> + clk_set_rate(i2s->clk_i2s, 12000000);
> + clk_prepare_enable(i2s->clk_i2s);
> +
> jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
> jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
>
>

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Re: [PATCH 4/4] sound: jz4740: Enable codec clock during dai_probe [ In reply to ]

Zubair.Kakakhel at imgtec

Jan 26, 2015, 3:30 AM

Post #3 of 4 (45 views)

Permalink

On 26/01/15 10:40, Lars-Peter Clausen wrote:
> On 01/26/2015 11:18 AM, Zubair Lutfullah Kakakhel wrote:
>> As we are moving away from platform to DT, we cant rely on the board
>> file to do this now. So enable it here.
>
> I don't understand this changelog. The board file never did this. The driver enables the clock in the startup() callback.

My bad.

I couldn't get the ci20 audio to work without this change.

I double checked. The clock is indeed enabled.

But the rate needs to be set for the ci20.

clk_set_rate(i2s->clk_i2s, 12000000);

Where should I put it? I couldn’t trace how the rate is set for the jz4740..

ZubairLK

>
>>
>> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
>> ---
>> sound/soc/jz4740/jz4740-i2s.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c
>> index 3c309fc..a7e4a7b 100644
>> --- a/sound/soc/jz4740/jz4740-i2s.c
>> +++ b/sound/soc/jz4740/jz4740-i2s.c
>> @@ -376,6 +376,10 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
>> JZ_AIC_CONF_I2S |
>> JZ_AIC_CONF_INTERNAL_CODEC;
>>
>> + /* enable codec sysclk */
>> + clk_set_rate(i2s->clk_i2s, 12000000);
>> + clk_prepare_enable(i2s->clk_i2s);
>> +
>> jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
>> jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
>>
>>
>
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Re: [alsa-devel] [PATCH 4/4] sound: jz4740: Enable codec clock during dai_probe [ In reply to ]

lars at metafoo

Jan 26, 2015, 3:42 AM

Post #4 of 4 (46 views)

Permalink

On 01/26/2015 12:30 PM, Zubair Lutfullah Kakakhel wrote:
>
> On 26/01/15 10:40, Lars-Peter Clausen wrote:
>> On 01/26/2015 11:18 AM, Zubair Lutfullah Kakakhel wrote:
>>> As we are moving away from platform to DT, we cant rely on the board
>>> file to do this now. So enable it here.
>>
>> I don't understand this changelog. The board file never did this. The driver enables the clock in the startup() callback.
>
> My bad.
>
> I couldn't get the ci20 audio to work without this change.
>
> I double checked. The clock is indeed enabled.
>
> But the rate needs to be set for the ci20.
>
> clk_set_rate(i2s->clk_i2s, 12000000);
>
> Where should I put it? I couldn’t trace how the rate is set for the jz4740..

There is no support for specifying clock rate defaults in the devicetree
itself. See commit 86be408bfbd8 ("clk: Support for clock parents and rates
assigned from device tree"). Since the preferred or correct clock rate will
be board specific this is probably where it should go.

- Lars

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