Mailing List Archive

* configure.ac (HAVE_GCC_INLINE_ASM_VAES_VPCLMUL): New.
* src/g10lib.h (HWF_INTEL_VAES_VPCLMUL): New.
* src/hwf-x86.c (detect_x86_gnuc): Check for VAES and VPCLMUL.
* src/hwfeatures.c (hwflist): Add "intel-vaes-vpclmul".
--

Detect support for VAES and VPCLMUL instruction sets, which allow
use of AES and PCLMUL instruction with 256-bit and 512-bit vector
registers.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
---
configure.ac | 32 ++++++++++++++++++++++++++++++++
src/g10lib.h | 1 +
src/hwf-x86.c | 11 +++++++++--
src/hwfeatures.c | 1 +
4 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index 61553ff8..564d361b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1609,6 +1609,31 @@ if test "$gcry_cv_gcc_inline_asm_avx2" = "yes" ; then
fi


+#
+# Check whether GCC inline assembler supports VAES and VPCLMUL instructions
+#
+AC_CACHE_CHECK([whether GCC inline assembler supports VAES and VPCLMUL instructions],
+ [gcry_cv_gcc_inline_asm_vaes_vpclmul],
+ [.if test "$mpi_cpu_arch" != "x86" ||
+ test "$try_asm_modules" != "yes" ; then
+ gcry_cv_gcc_inline_asm_vaes_vpclmul="n/a"
+ else
+ gcry_cv_gcc_inline_asm_vaes_vpclmul=no
+ AC_LINK_IFELSE([.AC_LANG_PROGRAM(
+ [.[.void a(void) {
+ __asm__("vaesenclast %%ymm7,%%ymm7,%%ymm1\n\t":::"cc");/*256-bit*/
+ __asm__("vaesenclast %%zmm7,%%zmm7,%%zmm1\n\t":::"cc");/*512-bit*/
+ __asm__("vpclmulqdq \$0,%%ymm7,%%ymm7,%%ymm1\n\t":::"cc");/*256-bit*/
+ __asm__("vpclmulqdq \$0,%%zmm7,%%zmm7,%%zmm1\n\t":::"cc");/*512-bit*/
+ }]], [ a(); ] )],
+ [gcry_cv_gcc_inline_asm_vaes_vpclmul=yes])
+ fi])
+if test "$gcry_cv_gcc_inline_asm_vaes_vpclmul" = "yes" ; then
+ AC_DEFINE(HAVE_GCC_INLINE_ASM_VAES_VPCLMUL,1,
+ [Defined if inline assembler supports VAES and VPCLMUL instructions])
+fi
+
+
#
# Check whether GCC inline assembler supports BMI2 instructions
#
@@ -2541,6 +2566,10 @@ if test "$found" = "1" ; then
# Build with the SSSE3 implementation
GCRYPT_CIPHERS="$GCRYPT_CIPHERS rijndael-ssse3-amd64.lo"
GCRYPT_CIPHERS="$GCRYPT_CIPHERS rijndael-ssse3-amd64-asm.lo"
+
+ # Build with the VAES/AVX2 implementation
+ GCRYPT_CIPHERS="$GCRYPT_CIPHERS rijndael-vaes.lo"
+ GCRYPT_CIPHERS="$GCRYPT_CIPHERS rijndael-vaes-avx2-amd64.lo"
;;
arm*-*-*)
# Build with the assembly implementation
@@ -2679,6 +2708,9 @@ if test "$found" = "1" ; then
if test x"$aesnisupport" = xyes ; then
# Build with the AES-NI/AVX2 implementation
GCRYPT_CIPHERS="$GCRYPT_CIPHERS camellia-aesni-avx2-amd64.lo"
+
+ # Build with the VAES/AVX2 implementation
+ GCRYPT_CIPHERS="$GCRYPT_CIPHERS camellia-vaes-avx2-amd64.lo"
fi
fi
fi
diff --git a/src/g10lib.h b/src/g10lib.h
index 243997eb..b0b73852 100644
--- a/src/g10lib.h
+++ b/src/g10lib.h
@@ -237,6 +237,7 @@ char **_gcry_strtokenize (const char *string, const char *delim);
#define HWF_INTEL_FAST_VPGATHER (1 << 14)
#define HWF_INTEL_RDTSC (1 << 15)
#define HWF_INTEL_SHAEXT (1 << 16)
+#define HWF_INTEL_VAES_VPCLMUL (1 << 17)

#elif defined(HAVE_CPU_ARCH_ARM)

diff --git a/src/hwf-x86.c b/src/hwf-x86.c
index 9a9ed6d3..91e4c411 100644
--- a/src/hwf-x86.c
+++ b/src/hwf-x86.c
@@ -372,7 +372,7 @@ detect_x86_gnuc (void)
if (max_cpuid_level >= 7 && (features & 0x00000001))
{
/* Get CPUID:7 contains further Intel feature flags. */
- get_cpuid(7, NULL, &features, NULL, NULL);
+ get_cpuid(7, NULL, &features, &features2, NULL);

/* Test bit 8 for BMI2. */
if (features & 0x00000100)
@@ -390,7 +390,14 @@ detect_x86_gnuc (void)

/* Test bit 29 for SHA Extensions. */
if (features & (1 << 29))
- result |= HWF_INTEL_SHAEXT;
+ result |= HWF_INTEL_SHAEXT;
+
+#if defined(ENABLE_AVX2_SUPPORT) && defined(ENABLE_AESNI_SUPPORT) && \
+ defined(ENABLE_PCLMUL_SUPPORT)
+ /* Test bit 9 for VAES and bit 10 for VPCLMULDQD */
+ if ((features2 & 0x00000200) && (features2 & 0x00000400))
+ result |= HWF_INTEL_VAES_VPCLMUL;
+#endif
}

return result;
diff --git a/src/hwfeatures.c b/src/hwfeatures.c
index db58d2a3..b47429bb 100644
--- a/src/hwfeatures.c
+++ b/src/hwfeatures.c
@@ -60,6 +60,7 @@ static struct
{ HWF_INTEL_FAST_VPGATHER, "intel-fast-vpgather" },
{ HWF_INTEL_RDTSC, "intel-rdtsc" },
{ HWF_INTEL_SHAEXT, "intel-shaext" },
+ { HWF_INTEL_VAES_VPCLMUL, "intel-vaes-vpclmul" },
#elif defined(HAVE_CPU_ARCH_ARM)
{ HWF_ARM_NEON, "arm-neon" },
{ HWF_ARM_AES, "arm-aes" },
--
2.27.0


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