Mailing List Archive

From https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87444 it appears that
l2-cache-size is a misnomer;
"A comment in driver-i386.c says:

/* Let the L3 replace the L2. This assumes inclusive caches
and single threaded program for now. */
if (level3.sizekb)
level2 = level3;"

"Probably the --param should be renamed to last-level-cache". So for the
CPUs below that means L3.

For the CPUs i have handy;
AMD 3900X
$ lscpu | grep '[23] cache'
L2 cache: 6 MiB (12 instances)
L3 cache: 64 MiB (4 instances)

AMD FX-8350
$ lscpu | grep '[23] cache'
L2 cache: 8 MiB (4 instances)
L3 cache: 8 MiB (1 instance)

Intel i5-1340P
$ lscpu | grep '[23] cache'
L2 cache: 9 MiB (6 instances)
L3 cache: 12 MiB (1 instance)

What is gcc using when using -march=native? (I use distcc so cant use
=native).
AMD 3900X
$ gcc -v -E -x c -march=native -mtune=native - < /dev/null 2>&1 | grep cc1
| sed 's/--param/\n--param/g' | grep '^--param l2-' | cut -d' ' -f1,2
--param l2-cache-size=512
>>> so this is the l2 size divided by the number of instances, 6MB / 12 =
512

AMD FX-8350
$ gcc -v -E -x c -march=native -mtune=native - < /dev/null 2>&1 | grep cc1
| sed 's/--param/\n--param/g' | grep '^--param l2-' | cut -d' ' -f1,2
--param l2-cache-size=2048
>>> so this is the l2 size divided by the number of instances, 8MB / 4 = 2MB

Intel i5-1340P
$ gcc -v -E -x c -march=native -mtune=native - < /dev/null 2>&1 | grep cc1
| sed 's/--param/\n--param/g' | grep '^--param l2-' | cut -d' ' -f1,2
--param l2-cache-size=12288
>>> this is the l3 size

So i'm thinking the Intel CPU l2-cache-size is correct but;
for the FX-8350 it should be l3 / instances, ie 8192 / 1 = 8192
for the 3900X it should be l3 / instances, ie 65536 / 4 = 16384

Am I correct?
Thanks