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Keir Fraser write on 2006$BG/(J11$B7n(J10$BF|(J 18:58:
> This is very skanky. Also I'm not sure why you write a 16-bit value
> into an 8-bit array entry at offset 0x40 (that's not even a BAR
> offset).
>
Thanks, the new patch fixed this.

> The base address used by Xen should be configured dynamically by qemu,
> perhaps for now via an hvm_op set_param hypercall. We need this for
> x86 as well, since PCI enumeration will move to hvmloader and
> trusting the base address to remain constant is foolish anyway.

We can see that this BAR is at offset 0x40, so it is a device-specific BAR rather than normal PCI BAR,
It should be ACPI driver(which is in Guest BIOS)'s responsibility to program this BAR rather than
PCI enumeration.

Current implementation is a little interesting. BAR is programmed by PCI enumeration, but this base address
in ACPI afdt table is hardcoded as 0xc010, that means if we add or remove a PCI device in qemu,
the base address allocated by PCI enumeration may change, while this base address in ACPI afdt table
is still 0xc010,( which is hardcoded). So shutdown may fail on IA32.

Since currently there is no ACPI driver in Guest Firmware both on IA32 and IPF,
It's reasonable that Qemu allocate the base address for ACPI hardware,(including hardcoding a base address).
IO addres below 0x1000 may used by legal device,
In IA32 side, PCI IO address is allocated from 0xc000,
In IPF side, PCI IO address is allocated from 0x2000.
So 0x1f40 is a safe address base.


In the future, if ACPI driver is implemented in Guest Firmware,
Definitely it shoulbe be ACPI driver to allocate the base address.
Then more logic should be added in qemu to allow ACPI driver to
program this BAR.


Anthony





>
> -- Keir
>
> On 10/11/06 09:35, "Xu, Anthony" <anthony.xu@intel.com> wrote:
>
>> Due to IPF Guest Firmware will enumerate PCI, shutdown in IPF
>> doesn't work This patch makes shutdown work for IPF.
>>
>> Tested on IA64 and IA32 side.
>>
>>
>> Signed-off-by, Anthony Xu < anthony.xu@intel.com >

On 13/11/06 8:18 am, "Xu, Anthony" <anthony.xu@intel.com> wrote:

> We can see that this BAR is at offset 0x40, so it is a device-specific BAR
> rather than normal PCI BAR,
> It should be ACPI driver(which is in Guest BIOS)'s responsibility to program
> this BAR rather than
> PCI enumeration.

Does this BAR not get set up properly in current qemu? It looks to me like
the existing code sets up this region as a standard PCI BAR? Maybe I need to
go read the PIIX spec.

-- Keir



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Keir Fraser write on 2006$BG/(J11$B7n(J13$BF|(J 16:29:
> On 13/11/06 8:18 am, "Xu, Anthony" <anthony.xu@intel.com> wrote:
>
>> We can see that this BAR is at offset 0x40, so it is a
>> device-specific BAR rather than normal PCI BAR, It should be ACPI
>> driver(which is in Guest BIOS)'s responsibility to program this BAR
>> rather than PCI enumeration.
>
> Does this BAR not get set up properly in current qemu?

Yes, this BAR get setup properly in current qemu by pci_bios_init,
But this BAR is passed to Guest OS thru ACPI afdt table,
this BAR is hardcoded to 0xc010 in ACPI afdt table.

So if pci_bios_init doesn't allocate 0xc010 to this BAR,
Shutdown can't work.


>It looks to me
> like the existing code sets up this region as a standard PCI BAR?
Yes, the existing code sets up this region as a standard PCI BAR


Anthony

> Maybe I need to go read the PIIX spec.
>
> -- Keir
>
>
>
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