Mailing List Archive

All of these are prediction-mode (i.e. CPL) based. They don't operate as
expected in PV context, and need emulating to have the intended behaviour.

Fixes: 4dd676070684 ("x86/spec-ctrl: Expose IPRED_CTRL to guests")
Fixes: 478e4787fa64 ("x86/spec-ctrl: Expose RRSBA_CTRL to guests")
Fixes: 583f1d095052 ("x86/spec-ctrl: Expose BHI_CTRL to guests")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
xen/include/public/arch-x86/cpufeatureset.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 3de7c0383f0e..6bb1ee3b0af4 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -311,10 +311,10 @@ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory

/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
-XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */
-XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */
+XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*S MSR_SPEC_CTRL.IPRED_DIS_* */
+XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*S MSR_SPEC_CTRL.RRSBA_DIS_* */
XEN_CPUFEATURE(DDP_CTRL, 13*32+ 3) /* MSR_SPEC_CTRL.DDP_DIS_U */
-XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*A MSR_SPEC_CTRL.BHI_DIS_S */
+XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*S MSR_SPEC_CTRL.BHI_DIS_S */
XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */

/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */

base-commit: 4be1fef1e6572c2be0bd378902ffb62a6e73faeb
--
2.30.2