Mailing List Archive

flight 10202 xen-unstable real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/10202/

Regressions :-(

Tests which did not succeed and are blocking:
test-amd64-amd64-xl-sedf 13 guest-localmigrate.2 fail REGR. vs. 10201

Tests which did not succeed, but are not blocking,
including regressions (tests previously passed) regarded as allowable:
test-amd64-i386-xend-winxpsp3 7 windows-install fail never pass
test-amd64-amd64-xl-win7-amd64 7 windows-install fail never pass
test-amd64-i386-xl-win7-amd64 7 windows-install fail never pass
test-amd64-amd64-xl-winxpsp3 7 windows-install fail never pass
test-amd64-i386-xl-winxpsp3-vcpus1 7 windows-install fail never pass
test-i386-i386-xl-winxpsp3 7 windows-install fail never pass
test-amd64-i386-rhel6hvm-intel 9 guest-start.2 fail never pass
test-amd64-i386-rhel6hvm-amd 9 guest-start.2 fail never pass
test-amd64-amd64-xl-pcipt-intel 9 guest-start fail never pass
test-amd64-amd64-xl-win 13 guest-stop fail never pass
test-amd64-i386-win-vcpus1 16 leak-check/check fail never pass
test-amd64-i386-win 16 leak-check/check fail never pass
test-i386-i386-win 16 leak-check/check fail never pass
test-amd64-i386-xl-win-vcpus1 13 guest-stop fail never pass
test-i386-i386-xl-win 13 guest-stop fail never pass
test-amd64-amd64-win 16 leak-check/check fail never pass

version targeted for testing:
xen 20c1c0ff9677
baseline version:
xen 62ff6a318c5d

------------------------------------------------------------
People who touched revisions under test:
Ian Campbell <ian.campbell@citrix.com>
Ian Jackson <ian.jackson@eu.citrix.com>
Jan Beulich <jbeulich@suse.com>
Keir Fraser <keir@xen.org>
Liu, Jinsong <jinsong.liu@intel.com>
------------------------------------------------------------

jobs:
build-amd64 pass
build-i386 pass
build-amd64-oldkern pass
build-i386-oldkern pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-i386-xl pass
test-i386-i386-xl pass
test-amd64-i386-rhel6hvm-amd fail
test-amd64-amd64-xl-win7-amd64 fail
test-amd64-i386-xl-win7-amd64 fail
test-amd64-i386-xl-credit2 pass
test-amd64-amd64-xl-pcipt-intel fail
test-amd64-i386-rhel6hvm-intel fail
test-amd64-i386-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-i386-pair pass
test-i386-i386-pair pass
test-amd64-amd64-pv pass
test-amd64-i386-pv pass
test-i386-i386-pv pass
test-amd64-amd64-xl-sedf fail
test-amd64-i386-win-vcpus1 fail
test-amd64-i386-xl-win-vcpus1 fail
test-amd64-i386-xl-winxpsp3-vcpus1 fail
test-amd64-amd64-win fail
test-amd64-i386-win fail
test-i386-i386-win fail
test-amd64-amd64-xl-win fail
test-i386-i386-xl-win fail
test-amd64-i386-xend-winxpsp3 fail
test-amd64-amd64-xl-winxpsp3 fail
test-i386-i386-xl-winxpsp3 fail


------------------------------------------------------------
sg-report-flight on woking.cam.xci-test.com
logs: /home/xc_osstest/logs
images: /home/xc_osstest/images

Logs, config files, etc. are available at
http://www.chiark.greenend.org.uk/~xensrcts/logs

Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Not pushing.

------------------------------------------------------------
changeset: 24279:20c1c0ff9677
tag: tip
user: Liu, Jinsong <jinsong.liu@intel.com>
date: Thu Dec 01 12:24:06 2011 +0100

X86: implement PCID/INVPCID for hvm

This patch handle PCID/INVPCID for hvm:

For hap hvm, we enable PCID/INVPCID, since no need to intercept
INVPCID, and we just set INVPCID non-root behavior as running natively;

For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate
INVPCID at vmm by setting INVPCID non-root behavior as vmexit.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>


changeset: 24278:d9cb04ed5539
user: Liu, Jinsong <jinsong.liu@intel.com>
date: Thu Dec 01 12:22:43 2011 +0100

X86: Disable PCID/INVPCID for dom0

PCID (Process-context identifier) is a facility by which a logical
processor may cache information for multiple linear-address spaces.
INVPCID is an new instruction to invalidate TLB. Refer latest Intel SDM
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

We disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 and pv
may result in performance regression, and it would trigger GP or UD
depending on whether platform suppport INVPCID or not.

This patch disables PCID/INVPCID for dom0.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>


changeset: 24277:1f6b58c8e1ba
user: Liu, Jinsong <jinsong.liu@intel.com>
date: Thu Dec 01 12:21:24 2011 +0100

X86: expose Intel new features to dom0

This patch expose Intel new features to dom0, including
FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>


changeset: 24276:89f727368169
user: Jan Beulich <jbeulich@suse.com>
date: Thu Dec 01 08:51:35 2011 +0100

x86/emulator: cleanup

Utilize some of the additions in the prior patches to clean up other
code:
- keep track of REP prefixes in only one variable
- use REX_W in a few more places (instead of a literal number)

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>


changeset: 24275:76ea126f2172
user: Jan Beulich <jbeulich@suse.com>
date: Thu Dec 01 08:50:49 2011 +0100

x86/emulator: properly handle lzcnt and tzcnt

These instructions are prefix selected flavors of bsf and bsr
respectively, and hence the presences of the F3 prefix must be handled
in the emulation code in order to avoid running into problems on newer
CPUs.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1058,6 +1058,9 @@ static bool_t vcpu_has(
return rc == X86EMUL_OKAY;
}

+#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops)
+#define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops)
+
#define vcpu_must_have(leaf, reg, bit) \
generate_exception_if(!vcpu_has(leaf, reg, bit, ctxt, ops), EXC_UD, -1)
#define vcpu_must_have_mmx() vcpu_must_have(0x00000001, EDX, 23)
@@ -4357,13 +4360,24 @@ x86_emulate(
dst.val = (uint8_t)src.val;
break;

- case 0xbc: /* bsf */ {
- int zf;
+ case 0xbc: /* bsf or tzcnt */ {
+ bool_t zf;
asm ( "bsf %2,%0; setz %b1"
: "=r" (dst.val), "=q" (zf)
- : "r" (src.val), "1" (0) );
+ : "r" (src.val) );
_regs.eflags &= ~EFLG_ZF;
- if ( zf )
+ if ( (rep_prefix == REPE_PREFIX) && vcpu_has_bmi1() )
+ {
+ _regs.eflags &= ~EFLG_CF;
+ if ( zf )
+ {
+ _regs.eflags |= EFLG_CF;
+ dst.val = op_bytes * 8;
+ }
+ else if ( !dst.val )
+ _regs.eflags |= EFLG_ZF;
+ }
+ else if ( zf )
{
_regs.eflags |= EFLG_ZF;
dst.type = OP_NONE;
@@ -4371,13 +4385,28 @@ x86_emulate(
break;
}

- case 0xbd: /* bsr */ {
- int zf;
+ case 0xbd: /* bsr or lzcnt */ {
+ bool_t zf;
asm ( "bsr %2,%0; setz %b1"
: "=r" (dst.val), "=q" (zf)
- : "r" (src.val), "1" (0) );
+ : "r" (src.val) );
_regs.eflags &= ~EFLG_ZF;
- if ( zf )
+ if ( (rep_prefix == REPE_PREFIX) && vcpu_has_lzcnt() )
+ {
+ _regs.eflags &= ~EFLG_CF;
+ if ( zf )
+ {
+ _regs.eflags |= EFLG_CF;
+ dst.val = op_bytes * 8;
+ }
+ else
+ {
+ dst.val = op_bytes * 8 - 1 - dst.val;
+ if ( !dst.val )
+ _regs.eflags |= EFLG_ZF;
+ }
+ }
+ else if ( zf )
{
_regs.eflags |= EFLG_ZF;
dst.type = OP_NONE;


changeset: 24274:07cf778d517f
user: Jan Beulich <jbeulich@suse.com>
date: Thu Dec 01 08:49:31 2011 +0100

x86/emulator: add emulation of SIMD FP moves

Clone the existing movq emulation to also support the most fundamental
SIMD FP moves.

Extend the testing code to also exercise these instructions.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>


changeset: 24273:73a5655c2ac5
user: Jan Beulich <jbeulich@suse.com>
date: Thu Dec 01 08:48:14 2011 +0100

x86/emulator: generalize movq emulation (SSE2 and AVX variants)

Extend the existing movq emulation to also support its SSE2 and AVX
variants, the latter implying the addition of VEX decoding. Fold the
read and write cases (as most of the logic is identical), and add
movntq and variants (as they're very similar).

Extend the testing code to also exercise these instructions.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>


changeset: 24272:62ff6a318c5d
user: Keir Fraser <keir@xen.org>
date: Wed Nov 30 16:59:58 2011 -0800

xenpaging: Fix c/s 23507:0a29c8c3ddf7 ("update machine_to_phys_mapping[] during page deallocation")

This patch clobbers page owner in free_heap_pages() before we are
finished using it. This means that a subsequent test to determine
whether it is safe to avoid safety TLB flushes incorrectly always
determines that it is safe to do so.

The fix is simple: we can defer the original patch's work until after
we are done with the page-owner field.

Thanks to Christian Limpach for spotting this one.

Signed-off-by: Keir Fraser <keir@xen.org>


========================================
commit 89daacab7035d408f32f2cb1acf68c96d6cbefed
Author: Ian Jackson <ian.jackson@eu.citrix.com>
Date: Mon Nov 28 17:16:52 2011 +0000

qemu-dm: open char devices "file:..." with O_APPEND

The "file:..." character open method is used by serial and parallel
ports, to divert the output to a file (and these devices never produce
any input). This is like a logfile, and so should be opened for
append.

In qemu-xen-unstable, this is used only for the qemu stderr by libxl.

Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

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