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[PATCH 2/6] X86: expose Intel new features to dom0
jinsong.liu at intel
Nov 24, 2011, 7:51 AM
Post #1 of 4 (157 views)
Permalink
X86: expose Intel new features to dom0

This patch expose Intel new features to dom0, including FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>

diff -r 38b25f3b2bca xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Thu Nov 17 17:54:17 2011 +0800
+++ b/xen/arch/x86/traps.c Thu Nov 17 18:06:01 2011 +0800
@@ -826,8 +826,11 @@ static void pv_cpuid(struct cpu_user_reg

case 0x00000007:
if ( regs->ecx == 0 )
- b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
- cpufeat_mask(X86_FEATURE_ERMS));
+ b &= (cpufeat_mask(X86_FEATURE_BMI1) |
+ cpufeat_mask(X86_FEATURE_AVX2) |
+ cpufeat_mask(X86_FEATURE_BMI2) |
+ cpufeat_mask(X86_FEATURE_ERMS) |
+ cpufeat_mask(X86_FEATURE_FSGSBASE));
else
b = 0;
a = c = d = 0;
diff -r 38b25f3b2bca xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Thu Nov 17 17:54:17 2011 +0800
+++ b/xen/include/asm-x86/cpufeature.h Thu Nov 17 18:06:01 2011 +0800
@@ -93,6 +93,7 @@
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
#define X86_FEATURE_CID (4*32+10) /* Context ID */
+#define X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
@@ -100,6 +101,7 @@
#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
#define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
#define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
+#define X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */
#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
#define X86_FEATURE_AES (4*32+25) /* AES instructions */
@@ -145,7 +147,10 @@

/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
+#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
+#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
#define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
#define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */

#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)

Attached Files:

Re: [PATCH 2/6] X86: expose Intel new features to dom0 [ In reply to ]
konrad at darnok
Nov 24, 2011, 8:28 AM
Post #2 of 4 (156 views)
Permalink
On Thu, Nov 24, 2011 at 11:51:37PM +0800, Liu, Jinsong wrote:
> X86: expose Intel new features to dom0
>
> This patch expose Intel new features to dom0, including FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.

And has it been tested with 3.1 pvops kernel?
Does it need a patch in the pvops kernel as well?
>
> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>
> diff -r 38b25f3b2bca xen/arch/x86/traps.c
> --- a/xen/arch/x86/traps.c Thu Nov 17 17:54:17 2011 +0800
> +++ b/xen/arch/x86/traps.c Thu Nov 17 18:06:01 2011 +0800
> @@ -826,8 +826,11 @@ static void pv_cpuid(struct cpu_user_reg
>
> case 0x00000007:
> if ( regs->ecx == 0 )
> - b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
> - cpufeat_mask(X86_FEATURE_ERMS));
> + b &= (cpufeat_mask(X86_FEATURE_BMI1) |
> + cpufeat_mask(X86_FEATURE_AVX2) |
> + cpufeat_mask(X86_FEATURE_BMI2) |
> + cpufeat_mask(X86_FEATURE_ERMS) |
> + cpufeat_mask(X86_FEATURE_FSGSBASE));
> else
> b = 0;
> a = c = d = 0;
> diff -r 38b25f3b2bca xen/include/asm-x86/cpufeature.h
> --- a/xen/include/asm-x86/cpufeature.h Thu Nov 17 17:54:17 2011 +0800
> +++ b/xen/include/asm-x86/cpufeature.h Thu Nov 17 18:06:01 2011 +0800
> @@ -93,6 +93,7 @@
> #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
> #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
> #define X86_FEATURE_CID (4*32+10) /* Context ID */
> +#define X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */
> #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
> #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
> #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
> @@ -100,6 +101,7 @@
> #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
> #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
> #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
> +#define X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */
> #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
> #define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
> #define X86_FEATURE_AES (4*32+25) /* AES instructions */
> @@ -145,7 +147,10 @@
>
> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
> #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
> +#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
> +#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
> #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection */
> +#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
> #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
>
> #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)

> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel


_______________________________________________
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Re: [PATCH 2/6] X86: expose Intel new features to dom0 [ In reply to ]
JBeulich at suse
Nov 24, 2011, 8:35 AM
Post #3 of 4 (158 views)
Permalink
>>> On 24.11.11 at 17:28, Konrad Rzeszutek Wilk <konrad@darnok.org> wrote:
> On Thu, Nov 24, 2011 at 11:51:37PM +0800, Liu, Jinsong wrote:
>> X86: expose Intel new features to dom0
>>
>> This patch expose Intel new features to dom0, including
> FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
>
> And has it been tested with 3.1 pvops kernel?
> Does it need a patch in the pvops kernel as well?

No - these are all unprivileged instructions not requiring any OS support.

Jan

>>
>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>>
>> diff -r 38b25f3b2bca xen/arch/x86/traps.c
>> --- a/xen/arch/x86/traps.c Thu Nov 17 17:54:17 2011 +0800
>> +++ b/xen/arch/x86/traps.c Thu Nov 17 18:06:01 2011 +0800
>> @@ -826,8 +826,11 @@ static void pv_cpuid(struct cpu_user_reg
>>
>> case 0x00000007:
>> if ( regs->ecx == 0 )
>> - b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
>> - cpufeat_mask(X86_FEATURE_ERMS));
>> + b &= (cpufeat_mask(X86_FEATURE_BMI1) |
>> + cpufeat_mask(X86_FEATURE_AVX2) |
>> + cpufeat_mask(X86_FEATURE_BMI2) |
>> + cpufeat_mask(X86_FEATURE_ERMS) |
>> + cpufeat_mask(X86_FEATURE_FSGSBASE));
>> else
>> b = 0;
>> a = c = d = 0;
>> diff -r 38b25f3b2bca xen/include/asm-x86/cpufeature.h
>> --- a/xen/include/asm-x86/cpufeature.h Thu Nov 17 17:54:17 2011 +0800
>> +++ b/xen/include/asm-x86/cpufeature.h Thu Nov 17 18:06:01 2011 +0800
>> @@ -93,6 +93,7 @@
>> #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
>> #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD
> Extensions-3 */
>> #define X86_FEATURE_CID (4*32+10) /* Context ID */
>> +#define X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */
>> #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
>> #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
>> #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
>> @@ -100,6 +101,7 @@
>> #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
>> #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
>> #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
>> +#define X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */
>> #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
>> #define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
>> #define X86_FEATURE_AES (4*32+25) /* AES instructions */
>> @@ -145,7 +147,10 @@
>>
>> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
>> #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
>> +#define X86_FEATURE_BMI1 (7*32+ 3) /* 1st bit manipulation extensions */
>> +#define X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */
>> #define X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection
> */
>> +#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */
>> #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
>>
>> #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel




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Re: [PATCH 2/6] X86: expose Intel new features to dom0 [ In reply to ]
jinsong.liu at intel
Nov 27, 2011, 2:09 AM
Post #4 of 4 (154 views)
Permalink
Jan Beulich wrote:
>>>> On 24.11.11 at 17:28, Konrad Rzeszutek Wilk <konrad@darnok.org>
>>>> wrote:
>> On Thu, Nov 24, 2011 at 11:51:37PM +0800, Liu, Jinsong wrote:
>>> X86: expose Intel new features to dom0
>>>
>>> This patch expose Intel new features to dom0, including
>> FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
>>
>> And has it been tested with 3.1 pvops kernel?
>> Does it need a patch in the pvops kernel as well?
>
> No - these are all unprivileged instructions not requiring any OS
> support.
>
> Jan
>

Yes, agree.

Thanks,
Jinsong

>>>
>>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
>>>
>>> diff -r 38b25f3b2bca xen/arch/x86/traps.c
>>> --- a/xen/arch/x86/traps.c Thu Nov 17 17:54:17 2011 +0800
>>> +++ b/xen/arch/x86/traps.c Thu Nov 17 18:06:01 2011 +0800
>>> @@ -826,8 +826,11 @@ static void pv_cpuid(struct cpu_user_reg
>>>
>>> case 0x00000007:
>>> if ( regs->ecx == 0 )
>>> - b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
>>> - cpufeat_mask(X86_FEATURE_ERMS));
>>> + b &= (cpufeat_mask(X86_FEATURE_BMI1) |
>>> + cpufeat_mask(X86_FEATURE_AVX2) |
>>> + cpufeat_mask(X86_FEATURE_BMI2) |
>>> + cpufeat_mask(X86_FEATURE_ERMS) |
>>> + cpufeat_mask(X86_FEATURE_FSGSBASE));
>>> else b = 0;
>>> a = c = d = 0;
>>> diff -r 38b25f3b2bca xen/include/asm-x86/cpufeature.h
>>> --- a/xen/include/asm-x86/cpufeature.h Thu Nov 17 17:54:17 2011
>>> +0800 +++ b/xen/include/asm-x86/cpufeature.h Thu Nov 17 18:06:01
>>> 2011 +0800 @@ -93,6 +93,7 @@ #define X86_FEATURE_TM2 (4*32+ 8) /*
>>> Thermal Monitor 2 */ #define X86_FEATURE_SSSE3 (4*32+ 9) /*
>>> Supplemental Streaming SIMD Extensions-3 */ #define
>>> X86_FEATURE_CID (4*32+10) /* Context ID */ +#define
>>> X86_FEATURE_FMA (4*32+12) /* Fused Multiply Add */ #define
>>> X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define
>>> X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
>>> #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
>>> @@ -100,6 +101,7 @@ #define X86_FEATURE_SSE4_1 (4*32+19) /*
>>> Streaming SIMD Extensions 4.1 */ #define
>>> X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
>>> #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */ +#define
>>> X86_FEATURE_MOVBE (4*32+22) /* movbe instruction */ #define
>>> X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ #define
>>> X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
>>> #define X86_FEATURE_AES (4*32+25) /* AES instructions */ @@ -145,7
>>> +147,10 @@
>>>
>>> /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx),
>>> word 7 */ #define X86_FEATURE_FSGSBASE (7*32+ 0) /*
>>> {RD,WR}{FS,GS}BASE instructions */ +#define X86_FEATURE_BMI1 (7*32+
>>> 3) /* 1st bit manipulation extensions */ +#define
>>> X86_FEATURE_AVX2 (7*32+ 5) /* AVX2 instructions */ #define
>>> X86_FEATURE_SMEP (7*32+ 7) /* Supervisor Mode Execution Protection
>>> */ +#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation
>>> extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP
>>> MOVSB/STOSB */
>>>
>>> #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
>>
>>> _______________________________________________
>>> Xen-devel mailing list
>>> Xen-devel@lists.xensource.com
>>> http://lists.xensource.com/xen-devel


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