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[PATCH 15/16] vmx: nest: capability reporting MSRs
qing.he at intel
Sep 8, 2010, 8:22 AM
Post #1 of 6 (321 views)
Permalink
handles VMX capability reporting MSRs.
Some features are masked so L1 would see a rather
simple configuration

Signed-off-by: Qing He <qing.he@intel.com>
Signed-off-by: Eddie Dong <eddie.dong@intel.com>

---

diff -r 694dcf6c3f06 xen/arch/x86/hvm/vmx/nest.c
--- a/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:14 2010 +0800
+++ b/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:39 2010 +0800
@@ -1352,3 +1352,91 @@

return bypass_l0;
}
+
+/*
+ * Capability reporting
+ */
+int vmx_nest_msr_read_intercept(unsigned int msr, u64 *msr_content)
+{
+ u32 eax, edx;
+ u64 data = 0;
+ int r = 1;
+ u32 mask = 0;
+
+ if ( !is_nested_avail(current->domain) )
+ return 0;
+
+ switch (msr) {
+ case MSR_IA32_VMX_BASIC:
+ rdmsr(msr, eax, edx);
+ data = edx;
+ data = (data & ~0x1fff) | 0x1000; /* request 4KB for guest VMCS */
+ data &= ~(1 << 23); /* disable TRUE_xxx_CTLS */
+ data = (data << 32) | VVMCS_REVISION; /* VVMCS revision */
+ break;
+ case MSR_IA32_VMX_PINBASED_CTLS:
+#define REMOVED_PIN_CONTROL_CAP (PIN_BASED_PREEMPT_TIMER)
+ rdmsr(msr, eax, edx);
+ data = edx;
+ data = (data << 32) | eax;
+ break;
+ case MSR_IA32_VMX_PROCBASED_CTLS:
+ rdmsr(msr, eax, edx);
+#define REMOVED_EXEC_CONTROL_CAP (CPU_BASED_TPR_SHADOW \
+ | CPU_BASED_ACTIVATE_MSR_BITMAP \
+ | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
+ data = edx & ~REMOVED_EXEC_CONTROL_CAP;
+ data = (data << 32) | eax;
+ break;
+ case MSR_IA32_VMX_EXIT_CTLS:
+ rdmsr(msr, eax, edx);
+#define REMOVED_EXIT_CONTROL_CAP (VM_EXIT_SAVE_GUEST_PAT \
+ | VM_EXIT_LOAD_HOST_PAT \
+ | VM_EXIT_SAVE_GUEST_EFER \
+ | VM_EXIT_LOAD_HOST_EFER \
+ | VM_EXIT_SAVE_PREEMPT_TIMER)
+ data = edx & ~REMOVED_EXIT_CONTROL_CAP;
+ data = (data << 32) | eax;
+ break;
+ case MSR_IA32_VMX_ENTRY_CTLS:
+ rdmsr(msr, eax, edx);
+#define REMOVED_ENTRY_CONTROL_CAP (VM_ENTRY_LOAD_GUEST_PAT \
+ | VM_ENTRY_LOAD_GUEST_EFER)
+ data = edx & ~REMOVED_ENTRY_CONTROL_CAP;
+ data = (data << 32) | eax;
+ break;
+ case MSR_IA32_VMX_PROCBASED_CTLS2:
+ mask = 0;
+
+ rdmsr(msr, eax, edx);
+ data = edx & mask;
+ data = (data << 32) | eax;
+ break;
+
+ /* pass through MSRs */
+ case IA32_FEATURE_CONTROL_MSR:
+ case MSR_IA32_VMX_MISC:
+ case MSR_IA32_VMX_CR0_FIXED0:
+ case MSR_IA32_VMX_CR0_FIXED1:
+ case MSR_IA32_VMX_CR4_FIXED0:
+ case MSR_IA32_VMX_CR4_FIXED1:
+ case MSR_IA32_VMX_VMCS_ENUM:
+ rdmsr(msr, eax, edx);
+ data = edx;
+ data = (data << 32) | eax;
+ break;
+
+ default:
+ r = 0;
+ break;
+ }
+
+ *msr_content = data;
+ return r;
+}
+
+int vmx_nest_msr_write_intercept(unsigned int msr, u64 msr_content)
+{
+ /* silently ignore for now */
+ return 1;
+}
diff -r 694dcf6c3f06 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 08 19:47:14 2010 +0800
+++ b/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 08 19:47:39 2010 +0800
@@ -1877,8 +1877,11 @@
*msr_content |= (u64)__vmread(GUEST_IA32_DEBUGCTL_HIGH) << 32;
#endif
break;
- case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
- goto gp_fault;
+ case IA32_FEATURE_CONTROL_MSR:
+ case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
+ if ( !vmx_nest_msr_read_intercept(msr, msr_content) )
+ goto gp_fault;
+ break;
case MSR_IA32_MISC_ENABLE:
rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content);
/* Debug Trace Store is not supported. */
@@ -2043,8 +2046,11 @@

break;
}
- case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
- goto gp_fault;
+ case IA32_FEATURE_CONTROL_MSR:
+ case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
+ if ( !vmx_nest_msr_write_intercept(msr, msr_content) )
+ goto gp_fault;
+ break;
default:
if ( vpmu_do_wrmsr(msr, msr_content) )
return X86EMUL_OKAY;
diff -r 694dcf6c3f06 xen/include/asm-x86/hvm/vmx/nest.h
--- a/xen/include/asm-x86/hvm/vmx/nest.h Wed Sep 08 19:47:14 2010 +0800
+++ b/xen/include/asm-x86/hvm/vmx/nest.h Wed Sep 08 19:47:39 2010 +0800
@@ -76,4 +76,9 @@
int vmx_nest_l2_vmexit_handler(struct cpu_user_regs *regs,
unsigned int exit_reason);

+int vmx_nest_msr_read_intercept(unsigned int msr,
+ u64 *msr_content);
+int vmx_nest_msr_write_intercept(unsigned int msr,
+ u64 msr_content);
+
#endif /* __ASM_X86_HVM_NEST_H__ */
diff -r 694dcf6c3f06 xen/include/asm-x86/hvm/vmx/vmcs.h
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h Wed Sep 08 19:47:14 2010 +0800
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h Wed Sep 08 19:47:39 2010 +0800
@@ -161,18 +161,23 @@
#define PIN_BASED_EXT_INTR_MASK 0x00000001
#define PIN_BASED_NMI_EXITING 0x00000008
#define PIN_BASED_VIRTUAL_NMIS 0x00000020
+#define PIN_BASED_PREEMPT_TIMER 0x00000040
extern u32 vmx_pin_based_exec_control;

#define VM_EXIT_IA32E_MODE 0x00000200
#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
#define VM_EXIT_SAVE_GUEST_PAT 0x00040000
#define VM_EXIT_LOAD_HOST_PAT 0x00080000
+#define VM_EXIT_SAVE_GUEST_EFER 0x00100000
+#define VM_EXIT_LOAD_HOST_EFER 0x00200000
+#define VM_EXIT_SAVE_PREEMPT_TIMER 0x00400000
extern u32 vmx_vmexit_control;

#define VM_ENTRY_IA32E_MODE 0x00000200
#define VM_ENTRY_SMM 0x00000400
#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
#define VM_ENTRY_LOAD_GUEST_PAT 0x00004000
+#define VM_ENTRY_LOAD_GUEST_EFER 0x00008000
extern u32 vmx_vmentry_control;

#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
diff -r 694dcf6c3f06 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Wed Sep 08 19:47:14 2010 +0800
+++ b/xen/include/asm-x86/msr-index.h Wed Sep 08 19:47:39 2010 +0800
@@ -172,6 +172,7 @@
#define MSR_IA32_VMX_CR0_FIXED1 0x487
#define MSR_IA32_VMX_CR4_FIXED0 0x488
#define MSR_IA32_VMX_CR4_FIXED1 0x489
+#define MSR_IA32_VMX_VMCS_ENUM 0x48a
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x48c
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d

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Re: [PATCH 15/16] vmx: nest: capability reporting MSRs [ In reply to ]
Tim.Deegan at citrix
Sep 13, 2010, 5:45 AM
Post #2 of 6 (325 views)
Permalink
At 16:22 +0100 on 08 Sep (1283962943), Qing He wrote:
> handles VMX capability reporting MSRs.
> Some features are masked so L1 would see a rather
> simple configuration

As I said last time, would it be better to whitelist features that we
know are safely virtualized?

> Signed-off-by: Qing He <qing.he@intel.com>
> Signed-off-by: Eddie Dong <eddie.dong@intel.com>
>
> ---
>
> diff -r 694dcf6c3f06 xen/arch/x86/hvm/vmx/nest.c
> --- a/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:39 2010 +0800
> @@ -1352,3 +1352,91 @@
>
> return bypass_l0;
> }
> +
> +/*
> + * Capability reporting
> + */
> +int vmx_nest_msr_read_intercept(unsigned int msr, u64 *msr_content)
> +{
> + u32 eax, edx;
> + u64 data = 0;
> + int r = 1;
> + u32 mask = 0;
> +
> + if ( !is_nested_avail(current->domain) )
> + return 0;
> +
> + switch (msr) {
> + case MSR_IA32_VMX_BASIC:
> + rdmsr(msr, eax, edx);
> + data = edx;
> + data = (data & ~0x1fff) | 0x1000; /* request 4KB for guest VMCS */
> + data &= ~(1 << 23); /* disable TRUE_xxx_CTLS */

Magic number - please use a macro to define it.

> + data = (data << 32) | VVMCS_REVISION; /* VVMCS revision */
> + break;
> + case MSR_IA32_VMX_PINBASED_CTLS:
> +#define REMOVED_PIN_CONTROL_CAP (PIN_BASED_PREEMPT_TIMER)

You define this mask but don't actually mask anything with it.

Cheers,

Tim.

--
Tim Deegan <Tim.Deegan@citrix.com>
Principal Software Engineer, XenServer Engineering
Citrix Systems UK Ltd. (Company #02937203, SL9 0BG)

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Re: [PATCH 15/16] vmx: nest: capability reporting MSRs [ In reply to ]
Christoph.Egger at amd
Sep 15, 2010, 3:05 AM
Post #3 of 6 (311 views)
Permalink
On Wednesday 08 September 2010 17:22:23 Qing He wrote:
> handles VMX capability reporting MSRs.
> Some features are masked so L1 would see a rather
> simple configuration
>
> Signed-off-by: Qing He <qing.he@intel.com>
> Signed-off-by: Eddie Dong <eddie.dong@intel.com>


Are there any vmx capability features that are read out via cpuid ?
If yes, then that code belongs into the tools patch.

In SVM the nestedhvm_vcpu_features hook is empty and for MSRs
there are already two msr hooks namely msr_read_intercept and
msr_write_intercept. I assume the functions below all called from there
directly or indirectly.

That renders the nestedhvm_vcpu_features hook useless and will remove it.

Christoph

> ---
>
> diff -r 694dcf6c3f06 xen/arch/x86/hvm/vmx/nest.c
> --- a/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/arch/x86/hvm/vmx/nest.c Wed Sep 08 19:47:39 2010 +0800
> @@ -1352,3 +1352,91 @@
>
> return bypass_l0;
> }
> +
> +/*
> + * Capability reporting
> + */
> +int vmx_nest_msr_read_intercept(unsigned int msr, u64 *msr_content)
> +{
> + u32 eax, edx;
> + u64 data = 0;
> + int r = 1;
> + u32 mask = 0;
> +
> + if ( !is_nested_avail(current->domain) )
> + return 0;
> +
> + switch (msr) {
> + case MSR_IA32_VMX_BASIC:
> + rdmsr(msr, eax, edx);
> + data = edx;
> + data = (data & ~0x1fff) | 0x1000; /* request 4KB for guest
> VMCS */ + data &= ~(1 << 23); /* disable
> TRUE_xxx_CTLS */ + data = (data << 32) | VVMCS_REVISION; /* VVMCS
> revision */ + break;
> + case MSR_IA32_VMX_PINBASED_CTLS:
> +#define REMOVED_PIN_CONTROL_CAP (PIN_BASED_PREEMPT_TIMER)
> + rdmsr(msr, eax, edx);
> + data = edx;
> + data = (data << 32) | eax;
> + break;
> + case MSR_IA32_VMX_PROCBASED_CTLS:
> + rdmsr(msr, eax, edx);
> +#define REMOVED_EXEC_CONTROL_CAP (CPU_BASED_TPR_SHADOW \
> + | CPU_BASED_ACTIVATE_MSR_BITMAP \
> + | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
> + data = edx & ~REMOVED_EXEC_CONTROL_CAP;
> + data = (data << 32) | eax;
> + break;
> + case MSR_IA32_VMX_EXIT_CTLS:
> + rdmsr(msr, eax, edx);
> +#define REMOVED_EXIT_CONTROL_CAP (VM_EXIT_SAVE_GUEST_PAT \
> + | VM_EXIT_LOAD_HOST_PAT \
> + | VM_EXIT_SAVE_GUEST_EFER \
> + | VM_EXIT_LOAD_HOST_EFER \
> + | VM_EXIT_SAVE_PREEMPT_TIMER)
> + data = edx & ~REMOVED_EXIT_CONTROL_CAP;
> + data = (data << 32) | eax;
> + break;
> + case MSR_IA32_VMX_ENTRY_CTLS:
> + rdmsr(msr, eax, edx);
> +#define REMOVED_ENTRY_CONTROL_CAP (VM_ENTRY_LOAD_GUEST_PAT \
> + | VM_ENTRY_LOAD_GUEST_EFER)
> + data = edx & ~REMOVED_ENTRY_CONTROL_CAP;
> + data = (data << 32) | eax;
> + break;
> + case MSR_IA32_VMX_PROCBASED_CTLS2:
> + mask = 0;
> +
> + rdmsr(msr, eax, edx);
> + data = edx & mask;
> + data = (data << 32) | eax;
> + break;
> +
> + /* pass through MSRs */
> + case IA32_FEATURE_CONTROL_MSR:
> + case MSR_IA32_VMX_MISC:
> + case MSR_IA32_VMX_CR0_FIXED0:
> + case MSR_IA32_VMX_CR0_FIXED1:
> + case MSR_IA32_VMX_CR4_FIXED0:
> + case MSR_IA32_VMX_CR4_FIXED1:
> + case MSR_IA32_VMX_VMCS_ENUM:
> + rdmsr(msr, eax, edx);
> + data = edx;
> + data = (data << 32) | eax;
> + break;
> +
> + default:
> + r = 0;
> + break;
> + }
> +
> + *msr_content = data;
> + return r;
> +}
> +
> +int vmx_nest_msr_write_intercept(unsigned int msr, u64 msr_content)
> +{
> + /* silently ignore for now */
> + return 1;
> +}
> diff -r 694dcf6c3f06 xen/arch/x86/hvm/vmx/vmx.c
> --- a/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/arch/x86/hvm/vmx/vmx.c Wed Sep 08 19:47:39 2010 +0800
> @@ -1877,8 +1877,11 @@
> *msr_content |= (u64)__vmread(GUEST_IA32_DEBUGCTL_HIGH) << 32;
> #endif
> break;
> - case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
> - goto gp_fault;
> + case IA32_FEATURE_CONTROL_MSR:
> + case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
> + if ( !vmx_nest_msr_read_intercept(msr, msr_content) )
> + goto gp_fault;
> + break;
> case MSR_IA32_MISC_ENABLE:
> rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content);
> /* Debug Trace Store is not supported. */
> @@ -2043,8 +2046,11 @@
>
> break;
> }
> - case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
> - goto gp_fault;
> + case IA32_FEATURE_CONTROL_MSR:
> + case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
> + if ( !vmx_nest_msr_write_intercept(msr, msr_content) )
> + goto gp_fault;
> + break;
> default:
> if ( vpmu_do_wrmsr(msr, msr_content) )
> return X86EMUL_OKAY;
> diff -r 694dcf6c3f06 xen/include/asm-x86/hvm/vmx/nest.h
> --- a/xen/include/asm-x86/hvm/vmx/nest.h Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/include/asm-x86/hvm/vmx/nest.h Wed Sep 08 19:47:39 2010 +0800
> @@ -76,4 +76,9 @@
> int vmx_nest_l2_vmexit_handler(struct cpu_user_regs *regs,
> unsigned int exit_reason);
>
> +int vmx_nest_msr_read_intercept(unsigned int msr,
> + u64 *msr_content);
> +int vmx_nest_msr_write_intercept(unsigned int msr,
> + u64 msr_content);
> +
> #endif /* __ASM_X86_HVM_NEST_H__ */
> diff -r 694dcf6c3f06 xen/include/asm-x86/hvm/vmx/vmcs.h
> --- a/xen/include/asm-x86/hvm/vmx/vmcs.h Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h Wed Sep 08 19:47:39 2010 +0800
> @@ -161,18 +161,23 @@
> #define PIN_BASED_EXT_INTR_MASK 0x00000001
> #define PIN_BASED_NMI_EXITING 0x00000008
> #define PIN_BASED_VIRTUAL_NMIS 0x00000020
> +#define PIN_BASED_PREEMPT_TIMER 0x00000040
> extern u32 vmx_pin_based_exec_control;
>
> #define VM_EXIT_IA32E_MODE 0x00000200
> #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
> #define VM_EXIT_SAVE_GUEST_PAT 0x00040000
> #define VM_EXIT_LOAD_HOST_PAT 0x00080000
> +#define VM_EXIT_SAVE_GUEST_EFER 0x00100000
> +#define VM_EXIT_LOAD_HOST_EFER 0x00200000
> +#define VM_EXIT_SAVE_PREEMPT_TIMER 0x00400000
> extern u32 vmx_vmexit_control;
>
> #define VM_ENTRY_IA32E_MODE 0x00000200
> #define VM_ENTRY_SMM 0x00000400
> #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
> #define VM_ENTRY_LOAD_GUEST_PAT 0x00004000
> +#define VM_ENTRY_LOAD_GUEST_EFER 0x00008000
> extern u32 vmx_vmentry_control;
>
> #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
> diff -r 694dcf6c3f06 xen/include/asm-x86/msr-index.h
> --- a/xen/include/asm-x86/msr-index.h Wed Sep 08 19:47:14 2010 +0800
> +++ b/xen/include/asm-x86/msr-index.h Wed Sep 08 19:47:39 2010 +0800
> @@ -172,6 +172,7 @@
> #define MSR_IA32_VMX_CR0_FIXED1 0x487
> #define MSR_IA32_VMX_CR4_FIXED0 0x488
> #define MSR_IA32_VMX_CR4_FIXED1 0x489
> +#define MSR_IA32_VMX_VMCS_ENUM 0x48a
> #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
> #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c
> #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d
>
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RE: [PATCH 15/16] vmx: nest: capability reporting MSRs [ In reply to ]
eddie.dong at intel
Sep 15, 2010, 7:28 AM
Post #4 of 6 (328 views)
Permalink
Christoph Egger wrote:
> On Wednesday 08 September 2010 17:22:23 Qing He wrote:
>> handles VMX capability reporting MSRs.
>> Some features are masked so L1 would see a rather
>> simple configuration
>>
>> Signed-off-by: Qing He <qing.he@intel.com>
>> Signed-off-by: Eddie Dong <eddie.dong@intel.com>
>
>
> Are there any vmx capability features that are read out via cpuid ?
> If yes, then that code belongs into the tools patch.

That is in 16.txt, you can include in your code. Once you fixed the MAX LEAF issue, I can ack that patch.

>
> In SVM the nestedhvm_vcpu_features hook is empty and for MSRs
> there are already two msr hooks namely msr_read_intercept and
> msr_write_intercept. I assume the functions below all called from
> there directly or indirectly.

No. this interception is for L1 guest.

>
> That renders the nestedhvm_vcpu_features hook useless and will remove
> it.

A step toward my wish of light weight wrapper, glad to see! The more you removed, the more I can ack, untill the point only those necessary APIs were left, such as nested EPT/NPT, heavily revisited interrupt injection API after removing the new namespace.

Thx, Eddie
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Re: [PATCH 15/16] vmx: nest: capability reporting MSRs [ In reply to ]
Christoph.Egger at amd
Sep 15, 2010, 7:45 AM
Post #5 of 6 (311 views)
Permalink
On Wednesday 15 September 2010 16:28:29 Dong, Eddie wrote:
> Christoph Egger wrote:
> > On Wednesday 08 September 2010 17:22:23 Qing He wrote:
> >> handles VMX capability reporting MSRs.
> >> Some features are masked so L1 would see a rather
> >> simple configuration
> >>
> >> Signed-off-by: Qing He <qing.he@intel.com>
> >> Signed-off-by: Eddie Dong <eddie.dong@intel.com>
> >
> > Are there any vmx capability features that are read out via cpuid ?
> > If yes, then that code belongs into the tools patch.
>
> That is in 16.txt, you can include in your code. Once you fixed the MAX
> LEAF issue, I can ack that patch.

Andre tried you to explain why the MAXLEAF change is not a problem.
Is there an other problem ?

>
> > In SVM the nestedhvm_vcpu_features hook is empty and for MSRs
> > there are already two msr hooks namely msr_read_intercept and
> > msr_write_intercept. I assume the functions below all called from
> > there directly or indirectly.
>
> No. this interception is for L1 guest.

Yes, that is how I understood.
What I mean is that you can call the functions from
vmx_msr_read_intercept/vmx_msr_write_intercept.

>
> > That renders the nestedhvm_vcpu_features hook useless and will remove
> > it.
>
> A step toward my wish of light weight wrapper, glad to see!

I would have removed it earlier, if you were telling me what I said above
which is what I want to know.

> The more you removed, the more I can ack, untill the point only those
> necessary APIs were left, such as nested EPT/NPT, heavily revisited
> interrupt injection API after removing the new namespace.

When you tell me which adjustments you exactly need I will do the changes
w/o breaking SVM, of course.

Christoph


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RE: [PATCH 15/16] vmx: nest: capability reporting MSRs [ In reply to ]
eddie.dong at intel
Sep 16, 2010, 7:10 AM
Post #6 of 6 (316 views)
Permalink
Christoph Egger wrote:
> On Wednesday 15 September 2010 16:28:29 Dong, Eddie wrote:
>> Christoph Egger wrote:
>>> On Wednesday 08 September 2010 17:22:23 Qing He wrote:
>>>> handles VMX capability reporting MSRs.
>>>> Some features are masked so L1 would see a rather
>>>> simple configuration
>>>>
>>>> Signed-off-by: Qing He <qing.he@intel.com>
>>>> Signed-off-by: Eddie Dong <eddie.dong@intel.com>
>>>
>>> Are there any vmx capability features that are read out via cpuid ?
>>> If yes, then that code belongs into the tools patch.
>>
>> That is in 16.txt, you can include in your code. Once you fixed the
>> MAX LEAF issue, I can ack that patch.
>
> Andre tried you to explain why the MAXLEAF change is not a problem.
> Is there an other problem ?
>

I replied to him and figured out the problem.

That is assuming Intel future processor won't implement more than 0x8...8 leaf, that is not good thing to do.
And the name of MAX_LEAF is then wrong to Intel CPU.
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