Mailing List Archive

# HG changeset patch
# User Keir Fraser <keir.fraser@citrix.com>
# Date 1276090710 -3600
# Node ID 65b27a094ec826a5a7db2d53e77988c3d76cef63
# Parent 706e6ba6074c4c12a2cde50451556c61fadefdd0
x86 mce: Use MSR_IA32_MCx_* macros consistently

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
---
xen/arch/x86/cpu/mcheck/amd_k8.c | 4 ++--
xen/arch/x86/cpu/mcheck/k7.c | 12 ++++++------
xen/arch/x86/cpu/mcheck/mce.c | 16 ++++++++--------
xen/arch/x86/cpu/mcheck/mce.h | 2 +-
xen/arch/x86/cpu/mcheck/mce_intel.c | 6 +++---
xen/arch/x86/cpu/mcheck/vmce.c | 2 +-
6 files changed, 21 insertions(+), 21 deletions(-)

diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/amd_k8.c
--- a/xen/arch/x86/cpu/mcheck/amd_k8.c Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/amd_k8.c Wed Jun 09 14:38:30 2010 +0100
@@ -90,8 +90,8 @@ enum mcheck_type amd_k8_mcheck_init(stru
mcequirk_amd_apply(quirkflag);
} else {
/* Enable error reporting of all errors */
- wrmsrl(MSR_IA32_MC0_CTL + 4 * i, 0xffffffffffffffffULL);
- wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+ wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
+ wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
break;
}
}
diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/k7.c
--- a/xen/arch/x86/cpu/mcheck/k7.c Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/k7.c Wed Jun 09 14:38:30 2010 +0100
@@ -32,7 +32,7 @@ static fastcall void k7_machine_check(st
smp_processor_id(), mcgsth, mcgstl);

for (i=1; i<nr_mce_banks; i++) {
- rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
+ rdmsr (MSR_IA32_MCx_STATUS(i),low, high);
if (high&(1<<31)) {
if (high & (1<<29))
recover |= 1;
@@ -41,16 +41,16 @@ static fastcall void k7_machine_check(st
printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
high &= ~(1<<31);
if (high & (1<<27)) {
- rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
+ rdmsr (MSR_IA32_MCx_MISC(i), alow, ahigh);
printk ("[%08x%08x]", ahigh, alow);
}
if (high & (1<<26)) {
- rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
+ rdmsr (MSR_IA32_MCx_ADDR(i), alow, ahigh);
printk (" at %08x%08x", ahigh, alow);
}
printk ("\n");
/* Clear it */
- wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+ wrmsr (MSR_IA32_MCx_STATUS(i), 0UL, 0UL);
/* Serialize */
wmb();
add_taint(TAINT_MACHINE_CHECK);
@@ -78,8 +78,8 @@ enum mcheck_type amd_k7_mcheck_init(stru
* as some Athlons cause spurious MCEs when its enabled. */
wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
for (i=1; i<nr_mce_banks; i++) {
- wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
- wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+ wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff);
+ wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0);
}

return mcheck_amd_k7;
diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.c Wed Jun 09 14:38:30 2010 +0100
@@ -164,7 +164,7 @@ static struct mcinfo_bank *mca_init_bank
}

memset(mib, 0, sizeof (struct mcinfo_bank));
- mca_rdmsrl(MSR_IA32_MC0_STATUS + bank * 4, mib->mc_status);
+ mca_rdmsrl(MSR_IA32_MCx_STATUS(bank), mib->mc_status);

mib->common.type = MC_TYPE_BANK;
mib->common.size = sizeof (struct mcinfo_bank);
@@ -172,11 +172,11 @@ static struct mcinfo_bank *mca_init_bank

addr = misc = 0;
if (mib->mc_status & MCi_STATUS_MISCV)
- mca_rdmsrl(MSR_IA32_MC0_MISC + 4 * bank, mib->mc_misc);
+ mca_rdmsrl(MSR_IA32_MCx_MISC(bank), mib->mc_misc);

if (mib->mc_status & MCi_STATUS_ADDRV)
{
- mca_rdmsrl(MSR_IA32_MC0_ADDR + 4 * bank, mib->mc_addr);
+ mca_rdmsrl(MSR_IA32_MCx_ADDR(bank), mib->mc_addr);

if (mfn_valid(paddr_to_pfn(mib->mc_addr))) {
struct domain *d;
@@ -287,7 +287,7 @@ mctelem_cookie_t mcheck_mca_logout(enum
if (!mcabanks_test(i, bankmask))
continue;

- mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status);
+ mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
if (!(status & MCi_STATUS_VAL))
continue; /* this bank has no valid telemetry */

@@ -345,7 +345,7 @@ mctelem_cookie_t mcheck_mca_logout(enum
/* By default, need_clear = 1 */
if (who != MCA_MCE_SCAN && need_clear)
/* Clear status */
- mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+ mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
else if ( who == MCA_MCE_SCAN && need_clear)
mcabanks_set(i, clear_bank);

@@ -605,10 +605,10 @@ void mcheck_mca_clearbanks(struct mca_ba
for (i = 0; i < 32 && i < nr_mce_banks; i++) {
if (!mcabanks_test(i, bankmask))
continue;
- mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status);
+ mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
if (!(status & MCi_STATUS_VAL))
continue;
- mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+ mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
}
}

@@ -1081,7 +1081,7 @@ void intpose_inval(unsigned int cpu_nr,

#define IS_MCA_BANKREG(r) \
((r) >= MSR_IA32_MC0_CTL && \
- (r) <= MSR_IA32_MC0_MISC + (nr_mce_banks - 1) * 4 && \
+ (r) <= MSR_IA32_MCx_MISC(nr_mce_banks - 1) && \
((r) - MSR_IA32_MC0_CTL) % 4 != 0) /* excludes MCi_CTL */

static int x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.h Wed Jun 09 14:38:30 2010 +0100
@@ -178,7 +178,7 @@ static inline int mce_bank_msr(uint32_t
static inline int mce_bank_msr(uint32_t msr)
{
if ( (msr > MSR_IA32_MC0_CTL2 &&
- msr < (MSR_IA32_MC0_CTL + 4 * nr_mce_banks - 1)) ||
+ msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) ||
mce_vendor_bank_msr(msr) )
return 1;
return 0;
diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c Wed Jun 09 14:38:30 2010 +0100
@@ -965,13 +965,13 @@ static void mce_init(void)
{
/* Some banks are shared across cores, use MCi_CTRL to judge whether
* this bank has been initialized by other cores already. */
- rdmsr(MSR_IA32_MC0_CTL + 4*i, l, h);
+ rdmsr(MSR_IA32_MCx_CTL(i), l, h);
if (!(l | h))
{
/* if ctl is 0, this bank is never initialized */
mce_printk(MCE_VERBOSE, "mce_init: init bank%d\n", i);
- wrmsr (MSR_IA32_MC0_CTL + 4*i, 0xffffffff, 0xffffffff);
- wrmsr (MSR_IA32_MC0_STATUS + 4*i, 0x0, 0x0);
+ wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff);
+ wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0);
}
}
if (firstbank) /* if cmci enabled, firstbank = 0 */
diff -r 706e6ba6074c -r 65b27a094ec8 xen/arch/x86/cpu/mcheck/vmce.c
--- a/xen/arch/x86/cpu/mcheck/vmce.c Wed Jun 09 14:36:11 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/vmce.c Wed Jun 09 14:38:30 2010 +0100
@@ -454,7 +454,7 @@ int vmce_init(struct cpuinfo_x86 *c)
/* Don't care banks before firstbank */
memset(h_mci_ctrl, 0xff, sizeof(h_mci_ctrl));
for (i = firstbank; i < nr_mce_banks; i++)
- rdmsrl(MSR_IA32_MC0_CTL + 4*i, h_mci_ctrl[i]);
+ rdmsrl(MSR_IA32_MCx_CTL(i), h_mci_ctrl[i]);
}

if (g_mcg_cap & MCG_CTL_P)

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