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# HG changeset patch
# User Keir Fraser <keir.fraser@citrix.com>
# Date 1269336931 0
# Node ID ec8f2e7dea44905eb86bb794516506451e4771cb
# Parent d6d3a704e7c1771919ee82798734d419c7af6ec9
x86: s3: ensure CR4.MCE is enabled after mcheck_init()

Changeset 21045: 7751288b1386 introduces a potential issue: CR4.MCE is
enabled before mcheck_init() -- thought looks I don't meet with an
actual issue with this, we'd better fix it.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
---
xen/arch/x86/acpi/power.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletion(-)

diff -r d6d3a704e7c1 -r ec8f2e7dea44 xen/arch/x86/acpi/power.c
--- a/xen/arch/x86/acpi/power.c Tue Mar 23 07:32:04 2010 +0000
+++ b/xen/arch/x86/acpi/power.c Tue Mar 23 09:35:31 2010 +0000
@@ -147,6 +147,7 @@ static int enter_state(u32 state)
{
unsigned long flags;
int error;
+ unsigned long cr4;

if ( (state <= ACPI_STATE_S0) || (state > ACPI_S_STATES_MAX) )
return -EINVAL;
@@ -201,13 +202,15 @@ static int enter_state(u32 state)
}

/* Restore CR4 and EFER from cached values. */
- write_cr4(read_cr4());
+ cr4 = read_cr4();
+ write_cr4(cr4 & ~X86_CR4_MCE);
if ( cpu_has_efer )
write_efer(read_efer());

device_power_up();

mcheck_init(&boot_cpu_data);
+ write_cr4(cr4);

printk(XENLOG_INFO "Finishing wakeup from ACPI S%d state.\n", state);


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