Mailing List Archive

# HG changeset patch
# User Keir Fraser <keir.fraser@citrix.com>
# Date 1221730793 -3600
# Node ID 104ceb3de2636e12bc177db0143796751dc98678
# Parent 71d3d3ac23b827e84e9b584bf04d49972107da5c
x86, amd, hvm: pass through one more cpuid cache description leaf

Add a missing CPUID leaf that contains AMD-specific cache info.
Without this, Windows can spin trying to prefetch memory buffers using
a stride length of zero.

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
---
tools/libxc/xc_cpuid_x86.c | 17 +++++++++++------
1 files changed, 11 insertions(+), 6 deletions(-)

diff -r 71d3d3ac23b8 -r 104ceb3de263 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Sep 18 10:32:40 2008 +0100
+++ b/tools/libxc/xc_cpuid_x86.c Thu Sep 18 10:39:53 2008 +0100
@@ -137,6 +137,10 @@ static void intel_xc_cpuid_policy(
(is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0));
break;
}
+
+ case 0x80000005:
+ regs[0] = regs[1] = regs[2] = 0;
+ break;
}
}

@@ -210,12 +214,13 @@ static void xc_cpuid_hvm_policy(
regs[1] = regs[2] = regs[3] = 0;
break;

- case 0x00000002:
- case 0x00000004:
- case 0x80000002:
- case 0x80000003:
- case 0x80000004:
- case 0x80000006:
+ case 0x00000002: /* Intel cache info (dumped by AMD policy) */
+ case 0x00000004: /* Intel cache info (dumped by AMD policy) */
+ case 0x80000002: /* Processor name string */
+ case 0x80000003: /* ... continued */
+ case 0x80000004: /* ... continued */
+ case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
+ case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
break;

default:

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