Mailing List Archive

# HG changeset patch
# User kaf24@firebug.cl.cam.ac.uk
# Node ID 9bde2889635cfcc1e2a823fde284132a8450cfad
# Parent 072d51860554ba37ed4c118ba818075dbb2ae382
Add SVM 32bit msr support (combined both 32bit with 64bit functions)
and enable vlapic for 64bit.

Signed-off-by: Tom Woller <thomas.woller@amd.com>

diff -r 072d51860554 -r 9bde2889635c xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c Wed Mar 1 22:38:18 2006
+++ b/xen/arch/x86/hvm/svm/svm.c Wed Mar 1 22:39:43 2006
@@ -247,6 +247,7 @@
void svm_restore_msrs(struct vcpu *v)
{
}
+#endif

#define IS_CANO_ADDRESS(add) 1

@@ -297,8 +298,13 @@
return 0;
}

+#ifdef __x86_64__
HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %lx\n",
msr_content);
+#else
+ HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %llx\n",
+ msr_content);
+#endif

regs->eax = msr_content & 0xffffffff;
regs->edx = msr_content >> 32;
@@ -311,12 +317,18 @@
struct vcpu *vc = current;
struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;

+#ifdef __x86_64__
HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx msr_content %lx\n",
regs->ecx, msr_content);
+#else
+ HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %x msr_content %llx\n",
+ regs->ecx, msr_content);
+#endif

switch (regs->ecx)
{
case MSR_EFER:
+#ifdef __x86_64__
if ((msr_content & EFER_LME) ^ test_bit(SVM_CPU_STATE_LME_ENABLED,
&vc->arch.hvm_svm.cpu_state))
{
@@ -337,6 +349,7 @@
if ((msr_content ^ vmcb->efer) & EFER_LME)
msr_content &= ~EFER_LME;
/* No update for LME/LMA since it have no effect */
+#endif
vmcb->efer = msr_content | EFER_SVME;
break;

@@ -382,18 +395,6 @@
}
return 1;
}
-
-#else
-static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
-{
- return 0;
-}
-
-static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
-{
- return 0;
-}
-#endif

void svm_store_cpu_guest_ctrl_regs(struct vcpu *v, unsigned long crs[8])
{
@@ -937,10 +938,8 @@

if (input == 1)
{
-#ifndef __x86_64__
if ( hvm_apic_support(v->domain) &&
!vlapic_global_enabled((VLAPIC(v))) )
-#endif
clear_bit(X86_FEATURE_APIC, &edx);

#if CONFIG_PAGING_LEVELS < 3

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