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# HG changeset patch
# User kaf24@firebug.cl.cam.ac.uk
# Node ID 22f14ec8e46c7a4c58dfde67abc11d18ef0c1f72
# Parent 42ff4f19d025670f0abc176c8622d9874f130947
Fix the issue when guest OS clear TS bit by mov to cr0 instead of
clts instruction for floating point context save and restore.
clts instruction is already handled in vmx exit handler while
vmx_set_cr0 has not handled it yet.

Signed-off-by: Xiaofeng Ling <xiaofeng.ling@intel.com>

xen-unstable cset: dc8122d906702a682dc896de44a32b7d27794586
committer: Robert Read <robert@xensource.com>

diff -r 42ff4f19d025 -r 22f14ec8e46c xen/arch/x86/vmx.c
--- a/xen/arch/x86/vmx.c Tue Dec 13 12:13:13 2005
+++ b/xen/arch/x86/vmx.c Wed Dec 14 10:47:16 2005
@@ -1086,11 +1086,21 @@
unsigned long eip;
int paging_enabled;
unsigned long vm_entry_value;
+ unsigned long old_cr0;

/*
* CR0: We don't want to lose PE and PG.
*/
- paging_enabled = vmx_paging_enabled(v);
+ __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
+ paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
+ /* If OS don't use clts to clear TS bit...*/
+ if((old_cr0 & X86_CR0_TS) && !(value & X86_CR0_TS))
+ {
+ clts();
+ setup_fpu(v);
+ }
+
+
__vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
__vmwrite(CR0_READ_SHADOW, value);


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