Mailing List Archive

# HG changeset patch
# User kaf24@firebug.cl.cam.ac.uk
# Node ID b438b8cb38f80bb8a4387c81c75c49b42c7d917f
# Parent 494243ba43b81a0aabba647bc12767ce5dd48179
Support VMX guest accesses to IA32_TIME_STAMP_COUNTER MSR.

Signed-off-by: Haifeng Xue <haifeng.xue@intel.com>

diff -r 494243ba43b8 -r b438b8cb38f8 xen/arch/x86/vmx.c
--- a/xen/arch/x86/vmx.c Tue Dec 13 16:02:55 2005
+++ b/xen/arch/x86/vmx.c Tue Dec 13 16:08:05 2005
@@ -1476,6 +1476,15 @@
(unsigned long)regs->ecx, (unsigned long)regs->eax,
(unsigned long)regs->edx);
switch (regs->ecx) {
+ case MSR_IA32_TIME_STAMP_COUNTER:
+ {
+ struct vmx_virpit *vpit;
+
+ rdtscll(msr_content);
+ vpit = &(v->domain->arch.vmx_platform.vmx_pit);
+ msr_content += vpit->shift;
+ break;
+ }
case MSR_IA32_SYSENTER_CS:
__vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
break;
@@ -1516,6 +1525,23 @@
msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);

switch (regs->ecx) {
+ case MSR_IA32_TIME_STAMP_COUNTER:
+ {
+ struct vmx_virpit *vpit;
+ u64 host_tsc, drift;
+
+ rdtscll(host_tsc);
+ vpit = &(v->domain->arch.vmx_platform.vmx_pit);
+ drift = v->arch.arch_vmx.tsc_offset - vpit->shift;
+ vpit->shift = msr_content - host_tsc;
+ v->arch.arch_vmx.tsc_offset = vpit->shift + drift;
+ __vmwrite(TSC_OFFSET, vpit->shift);
+
+#if defined (__i386__)
+ __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>>32));
+#endif
+ break;
+ }
case MSR_IA32_SYSENTER_CS:
__vmwrite(GUEST_SYSENTER_CS, msr_content);
break;
diff -r 494243ba43b8 -r b438b8cb38f8 xen/arch/x86/vmx_io.c
--- a/xen/arch/x86/vmx_io.c Tue Dec 13 16:02:55 2005
+++ b/xen/arch/x86/vmx_io.c Tue Dec 13 16:08:05 2005
@@ -801,11 +801,11 @@
drift = vpit->period_cycles * vpit->pending_intr_nr;
else
drift = 0;
- drift = v->arch.arch_vmx.tsc_offset - drift;
- __vmwrite(TSC_OFFSET, drift);
+ vpit->shift = v->arch.arch_vmx.tsc_offset - drift;
+ __vmwrite(TSC_OFFSET, vpit->shift);

#if defined (__i386__)
- __vmwrite(TSC_OFFSET_HIGH, (drift >> 32));
+ __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>> 32));
#endif
}

diff -r 494243ba43b8 -r b438b8cb38f8 xen/include/asm-x86/msr.h
--- a/xen/include/asm-x86/msr.h Tue Dec 13 16:02:55 2005
+++ b/xen/include/asm-x86/msr.h Tue Dec 13 16:08:05 2005
@@ -88,6 +88,7 @@
/* Intel defined MSRs. */
#define MSR_IA32_P5_MC_ADDR 0
#define MSR_IA32_P5_MC_TYPE 1
+#define MSR_IA32_TIME_STAMP_COUNTER 0x10
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_IA32_EBL_CR_POWERON 0x2a

diff -r 494243ba43b8 -r b438b8cb38f8 xen/include/asm-x86/vmx_vpit.h
--- a/xen/include/asm-x86/vmx_vpit.h Tue Dec 13 16:02:55 2005
+++ b/xen/include/asm-x86/vmx_vpit.h Tue Dec 13 16:08:05 2005
@@ -21,6 +21,7 @@
/* for simulation of counter 0 in mode 2*/
u64 period_cycles; /* pit frequency in cpu cycles */
u64 inject_point; /* the time inject virt intr */
+ u64 shift; /* save the value of offset - drift */
s_time_t scheduled; /* scheduled timer interrupt */
struct ac_timer pit_timer; /* periodic timer for mode 2*/
unsigned int channel; /* the pit channel, counter 0~2 */

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