On Wed, Feb 16, 2000 at 08:01:47AM +0000, Tigran Aivazian wrote:
> Also, more importantly, Intel manual says "the update must run in the
> early stages of POST and always before L2 cache controllers are
> initialized". I ignored it and it still worked fine.
I don't know much about intel microcode, but perhaps a microcode update
_may_ change cache handling. So it might work with every microcode
update available now (because Intel didn't make any incompatible
changes), but may fail with the next one.
Jan
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/
> Also, more importantly, Intel manual says "the update must run in the
> early stages of POST and always before L2 cache controllers are
> initialized". I ignored it and it still worked fine.
I don't know much about intel microcode, but perhaps a microcode update
_may_ change cache handling. So it might work with every microcode
update available now (because Intel didn't make any incompatible
changes), but may fail with the next one.
Jan
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/