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[RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
jan.dakinevich at salutedevices
Mar 27, 2024, 6:08 PM
Post #1 of 6 (33 views)
Permalink
Add device tree bindings for A1 SoC audio clock and reset controllers.

Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
---
.../bindings/clock/amlogic,a1-audio-clkc.yaml | 141 ++++++++++++++++++
.../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 +++++++++++++++
.../reset/amlogic,meson-a1-audio-reset.h | 29 ++++
3 files changed, 292 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h

diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
new file mode 100644
index 000000000000..1c9ef3292f3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic A1 Audio Clock Control Unit and Reset Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jan Dakinevich <jan.dakinevich@salutedevices.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,a1-audio-clkc
+ - amlogic,a1-audio2-clkc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 6
+ maxItems: 7
+
+ clock-names:
+ minItems: 6
+ maxItems: 7
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,a1-audio-clkc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: input core clock
+ - description: input main peripheral bus clock
+ - description: input dds_in
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input hifi_pll
+ - description: input oscillator (usually at 24MHz)
+ clocks-names:
+ items:
+ - const: core
+ - const: pclk
+ - const: dds_in
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: hifi_pll
+ - const: xtal
+ required:
+ - '#reset-cells'
+ else:
+ properties:
+ clocks:
+ items:
+ - description: input main peripheral bus clock
+ - description: input dds_in
+ - description: input fixed pll div2
+ - description: input fixed pll div3
+ - description: input hifi_pll
+ - description: input oscillator (usually at 24MHz)
+ clock-names:
+ items:
+ - const: pclk
+ - const: dds_in
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: hifi_pll
+ - const: xtal
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
+ #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
+ #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
+ audio {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_audio: audio-clock-controller@fe050000 {
+ compatible = "amlogic,a1-audio-clkc";
+ reg = <0x0 0xfe050000 0x0 0xb0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
+ <&clkc_periphs CLKID_AUDIO>,
+ <&clkc_periphs CLKID_DDS_IN>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "core",
+ "pclk",
+ "dds_in",
+ "fclk_div2",
+ "fclk_div3",
+ "hifi_pll",
+ "xtal";
+ };
+
+ clkc_audio2: audio-clock-controller@fe054800 {
+ compatible = "amlogic,a1-audio2-clkc";
+ reg = <0x0 0xfe054800 0x0 0x20>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_AUDIO>,
+ <&clkc_periphs CLKID_DDS_IN>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "pclk",
+ "dds_in",
+ "fclk_div2",
+ "fclk_div3",
+ "hifi_pll",
+ "xtal";
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
new file mode 100644
index 000000000000..b30df3b1ae08
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef __A1_AUDIO_CLKC_BINDINGS_H
+#define __A1_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB 1
+#define AUD_CLKID_TDMIN_A 2
+#define AUD_CLKID_TDMIN_B 3
+#define AUD_CLKID_TDMIN_LB 4
+#define AUD_CLKID_LOOPBACK 5
+#define AUD_CLKID_TDMOUT_A 6
+#define AUD_CLKID_TDMOUT_B 7
+#define AUD_CLKID_FRDDR_A 8
+#define AUD_CLKID_FRDDR_B 9
+#define AUD_CLKID_TODDR_A 10
+#define AUD_CLKID_TODDR_B 11
+#define AUD_CLKID_SPDIFIN 12
+#define AUD_CLKID_RESAMPLE 13
+#define AUD_CLKID_EQDRC 14
+#define AUD_CLKID_LOCKER 15
+#define AUD_CLKID_MST_A_MCLK_SEL 16
+#define AUD_CLKID_MST_A_MCLK_DIV 17
+#define AUD_CLKID_MST_A_MCLK 18
+#define AUD_CLKID_MST_B_MCLK_SEL 19
+#define AUD_CLKID_MST_B_MCLK_DIV 20
+#define AUD_CLKID_MST_B_MCLK 21
+#define AUD_CLKID_MST_C_MCLK_SEL 22
+#define AUD_CLKID_MST_C_MCLK_DIV 23
+#define AUD_CLKID_MST_C_MCLK 24
+#define AUD_CLKID_MST_D_MCLK_SEL 25
+#define AUD_CLKID_MST_D_MCLK_DIV 26
+#define AUD_CLKID_MST_D_MCLK 27
+#define AUD_CLKID_SPDIFIN_CLK_SEL 28
+#define AUD_CLKID_SPDIFIN_CLK_DIV 29
+#define AUD_CLKID_SPDIFIN_CLK 30
+#define AUD_CLKID_RESAMPLE_CLK_SEL 31
+#define AUD_CLKID_RESAMPLE_CLK_DIV 32
+#define AUD_CLKID_RESAMPLE_CLK 33
+#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
+#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
+#define AUD_CLKID_LOCKER_IN_CLK 36
+#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
+#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
+#define AUD_CLKID_LOCKER_OUT_CLK 39
+#define AUD_CLKID_EQDRC_CLK_SEL 40
+#define AUD_CLKID_EQDRC_CLK_DIV 41
+#define AUD_CLKID_EQDRC_CLK 42
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
+#define AUD_CLKID_MST_A_SCLK_DIV 44
+#define AUD_CLKID_MST_A_SCLK_POST_EN 45
+#define AUD_CLKID_MST_A_SCLK 46
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
+#define AUD_CLKID_MST_B_SCLK_DIV 48
+#define AUD_CLKID_MST_B_SCLK_POST_EN 49
+#define AUD_CLKID_MST_B_SCLK 50
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
+#define AUD_CLKID_MST_C_SCLK_DIV 52
+#define AUD_CLKID_MST_C_SCLK_POST_EN 53
+#define AUD_CLKID_MST_C_SCLK 54
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
+#define AUD_CLKID_MST_D_SCLK_DIV 56
+#define AUD_CLKID_MST_D_SCLK_POST_EN 57
+#define AUD_CLKID_MST_D_SCLK 58
+#define AUD_CLKID_MST_A_LRCLK_DIV 59
+#define AUD_CLKID_MST_A_LRCLK 60
+#define AUD_CLKID_MST_B_LRCLK_DIV 61
+#define AUD_CLKID_MST_B_LRCLK 62
+#define AUD_CLKID_MST_C_LRCLK_DIV 63
+#define AUD_CLKID_MST_C_LRCLK 64
+#define AUD_CLKID_MST_D_LRCLK_DIV 65
+#define AUD_CLKID_MST_D_LRCLK 66
+#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
+#define AUD_CLKID_TDMIN_A_SCLK 70
+#define AUD_CLKID_TDMIN_A_LRCLK 71
+#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
+#define AUD_CLKID_TDMIN_B_SCLK 75
+#define AUD_CLKID_TDMIN_B_LRCLK 76
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
+#define AUD_CLKID_TDMIN_LB_SCLK 80
+#define AUD_CLKID_TDMIN_LB_LRCLK 81
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
+#define AUD_CLKID_TDMOUT_A_SCLK 85
+#define AUD_CLKID_TDMOUT_A_LRCLK 86
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
+#define AUD_CLKID_TDMOUT_B_SCLK 90
+#define AUD_CLKID_TDMOUT_B_LRCLK 91
+
+#define AUD2_CLKID_DDR_ARB 1
+#define AUD2_CLKID_PDM 2
+#define AUD2_CLKID_TDMIN_VAD 3
+#define AUD2_CLKID_TODDR_VAD 4
+#define AUD2_CLKID_VAD 5
+#define AUD2_CLKID_AUDIOTOP 6
+#define AUD2_CLKID_VAD_MCLK_SEL 7
+#define AUD2_CLKID_VAD_MCLK_DIV 8
+#define AUD2_CLKID_VAD_MCLK 9
+#define AUD2_CLKID_VAD_CLK_SEL 10
+#define AUD2_CLKID_VAD_CLK_DIV 11
+#define AUD2_CLKID_VAD_CLK 12
+#define AUD2_CLKID_PDM_DCLK_SEL 13
+#define AUD2_CLKID_PDM_DCLK_DIV 14
+#define AUD2_CLKID_PDM_DCLK 15
+#define AUD2_CLKID_PDM_SYSCLK_SEL 16
+#define AUD2_CLKID_PDM_SYSCLK_DIV 17
+#define AUD2_CLKID_PDM_SYSCLK 18
+
+#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 000000000000..653fddba1d8f
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB 0
+#define AUD_RESET_TDMIN_A 1
+#define AUD_RESET_TDMIN_B 2
+#define AUD_RESET_TDMIN_LB 3
+#define AUD_RESET_LOOPBACK 4
+#define AUD_RESET_TDMOUT_A 5
+#define AUD_RESET_TDMOUT_B 6
+#define AUD_RESET_FRDDR_A 7
+#define AUD_RESET_FRDDR_B 8
+#define AUD_RESET_TODDR_A 9
+#define AUD_RESET_TODDR_B 10
+#define AUD_RESET_SPDIFIN 11
+#define AUD_RESET_RESAMPLE 12
+#define AUD_RESET_EQDRC 13
+#define AUD_RESET_LOCKER 14
+#define AUD_RESET_TOACODEC 30
+#define AUD_RESET_CLKTREE 31
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
--
2.34.1
Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver [ In reply to ]
krzysztof.kozlowski at linaro
Mar 28, 2024, 2:01 AM
Post #2 of 6 (30 views)
Permalink
On 28/03/2024 02:08, Jan Dakinevich wrote:
> Add device tree bindings for A1 SoC audio clock and reset controllers.
>
> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> ---

> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,a1-audio-clkc
> + - amlogic,a1-audio2-clkc

What is "2"?

> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 6
> + maxItems: 7
> +
> + clock-names:
> + minItems: 6
> + maxItems: 7
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,a1-audio-clkc
> + then:
> + properties:
> + clocks:
> + items:
> + - description: input core clock
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clocks-names:
> + items:
> + - const: core
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal
> + required:
> + - '#reset-cells'
> + else:
> + properties:
> + clocks:
> + items:
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clock-names:
> + items:
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal

#reset-cells: false

> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
> + audio {

If there is going to be any new version/resend:
soc {

> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clkc_audio: audio-clock-controller@fe050000 {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
So: clock-controller

> + compatible = "amlogic,a1-audio-clkc";
> + reg = <0x0 0xfe050000 0x0 0xb0>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
> + <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "core",
> + "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> +
> + clkc_audio2: audio-clock-controller@fe054800 {

clock-controller
(so I expect resend)

> + compatible = "amlogic,a1-audio2-clkc";
> + reg = <0x0 0xfe054800 0x0 0x20>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> + };
> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> new file mode 100644
> index 000000000000..b30df3b1ae08
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> @@ -0,0 +1,122 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + *
> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> + */
> +
> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
> +#define __A1_AUDIO_CLKC_BINDINGS_H
> +
> +#define AUD_CLKID_DDR_ARB 1
> +#define AUD_CLKID_TDMIN_A 2
> +#define AUD_CLKID_TDMIN_B 3
> +#define AUD_CLKID_TDMIN_LB 4

Why both clock controllers have the same clocks? This is confusing. It
seems you split same block into two!

Best regards,
Krzysztof
Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver [ In reply to ]
krzysztof.kozlowski at linaro
Mar 28, 2024, 2:02 AM
Post #3 of 6 (30 views)
Permalink
On 28/03/2024 10:01, Krzysztof Kozlowski wrote:
>> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> new file mode 100644
>> index 000000000000..b30df3b1ae08
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> @@ -0,0 +1,122 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
>> +#define __A1_AUDIO_CLKC_BINDINGS_H
>> +
>> +#define AUD_CLKID_DDR_ARB 1
>> +#define AUD_CLKID_TDMIN_A 2
>> +#define AUD_CLKID_TDMIN_B 3
>> +#define AUD_CLKID_TDMIN_LB 4
>
> Why both clock controllers have the same clocks? This is confusing. It
> seems you split same block into two!

Ah, no, I missed there are IDs for second clock controller. It's fine.

Best regards,
Krzysztof
Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver [ In reply to ]
jan.dakinevich at salutedevices
Mar 28, 2024, 12:43 PM
Post #4 of 6 (27 views)
Permalink
On 3/28/24 12:01, Krzysztof Kozlowski wrote:
> On 28/03/2024 02:08, Jan Dakinevich wrote:
>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>
>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> ---
>
>> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <neil.armstrong@linaro.org>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + - amlogic,a1-audio2-clkc
>
> What is "2"?
>

This is the second clock controller. I couldn't think of a better name.

> If there is going to be any new version/resend:

Definitely, this is not the final version. Thank you for comments!


>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 6
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 6
>> + maxItems: 7
>> +
>> +required:
>> + - compatible
>> + - '#clock-cells'
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input core clock
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clocks-names:
>> + items:
>> + - const: core
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>> + required:
>> + - '#reset-cells'
>> + else:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clock-names:
>> + items:
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>
> #reset-cells: false
>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>> + audio {
>
> If there is going to be any new version/resend:
> soc {
>
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clkc_audio: audio-clock-controller@fe050000 {
>
> Node names should be generic. See also an explanation and list of
> examples (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> So: clock-controller
>
>> + compatible = "amlogic,a1-audio-clkc";
>> + reg = <0x0 0xfe050000 0x0 0xb0>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
>> + <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "core",
>> + "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> +
>> + clkc_audio2: audio-clock-controller@fe054800 {
>
> clock-controller
> (so I expect resend)
>
>> + compatible = "amlogic,a1-audio2-clkc";
>> + reg = <0x0 0xfe054800 0x0 0x20>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> new file mode 100644
>> index 000000000000..b30df3b1ae08
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> @@ -0,0 +1,122 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
>> +#define __A1_AUDIO_CLKC_BINDINGS_H
>> +
>> +#define AUD_CLKID_DDR_ARB 1
>> +#define AUD_CLKID_TDMIN_A 2
>> +#define AUD_CLKID_TDMIN_B 3
>> +#define AUD_CLKID_TDMIN_LB 4
>
> Why both clock controllers have the same clocks? This is confusing. It
> seems you split same block into two!
>
> Best regards,
> Krzysztof
>

--
Best regards
Jan Dakinevich
Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver [ In reply to ]
jbrunet at baylibre
Mar 29, 2024, 5:24 AM
Post #5 of 6 (27 views)
Permalink
On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:

> Add device tree bindings for A1 SoC audio clock and reset controllers.
>
> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> ---
> .../bindings/clock/amlogic,a1-audio-clkc.yaml | 141 ++++++++++++++++++
> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 +++++++++++++++
> .../reset/amlogic,meson-a1-audio-reset.h | 29 ++++
> 3 files changed, 292 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> new file mode 100644
> index 000000000000..1c9ef3292f3c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,a1-audio-clkc
> + - amlogic,a1-audio2-clkc
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 6
> + maxItems: 7
> +
> + clock-names:
> + minItems: 6
> + maxItems: 7
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,a1-audio-clkc
> + then:
> + properties:
> + clocks:
> + items:
> + - description: input core clock
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clocks-names:
> + items:
> + - const: core
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal
> + required:
> + - '#reset-cells'
> + else:
> + properties:
> + clocks:
> + items:
> + - description: input main peripheral bus clock
> + - description: input dds_in
> + - description: input fixed pll div2
> + - description: input fixed pll div3
> + - description: input hifi_pll
> + - description: input oscillator (usually at 24MHz)
> + clock-names:
> + items:
> + - const: pclk
> + - const: dds_in
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: hifi_pll
> + - const: xtal

All the optional slave clock inputs are missing from this dcoumentation..
They need to be documentated as well

> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
> + audio {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clkc_audio: audio-clock-controller@fe050000 {
> + compatible = "amlogic,a1-audio-clkc";
> + reg = <0x0 0xfe050000 0x0 0xb0>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
> + <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "core",
> + "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> +
> + clkc_audio2: audio-clock-controller@fe054800 {
> + compatible = "amlogic,a1-audio2-clkc";
> + reg = <0x0 0xfe054800 0x0 0x20>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs CLKID_AUDIO>,
> + <&clkc_periphs CLKID_DDS_IN>,
> + <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "pclk",
> + "dds_in",
> + "fclk_div2",
> + "fclk_div3",
> + "hifi_pll",
> + "xtal";
> + };
> + };
> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> new file mode 100644
> index 000000000000..b30df3b1ae08
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
> @@ -0,0 +1,122 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + *
> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> + */
> +
> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
> +#define __A1_AUDIO_CLKC_BINDINGS_H
> +
> +#define AUD_CLKID_DDR_ARB 1
> +#define AUD_CLKID_TDMIN_A 2
> +#define AUD_CLKID_TDMIN_B 3
> +#define AUD_CLKID_TDMIN_LB 4
> +#define AUD_CLKID_LOOPBACK 5
> +#define AUD_CLKID_TDMOUT_A 6
> +#define AUD_CLKID_TDMOUT_B 7
> +#define AUD_CLKID_FRDDR_A 8
> +#define AUD_CLKID_FRDDR_B 9
> +#define AUD_CLKID_TODDR_A 10
> +#define AUD_CLKID_TODDR_B 11
> +#define AUD_CLKID_SPDIFIN 12
> +#define AUD_CLKID_RESAMPLE 13
> +#define AUD_CLKID_EQDRC 14
> +#define AUD_CLKID_LOCKER 15
> +#define AUD_CLKID_MST_A_MCLK_SEL 16
> +#define AUD_CLKID_MST_A_MCLK_DIV 17
> +#define AUD_CLKID_MST_A_MCLK 18
> +#define AUD_CLKID_MST_B_MCLK_SEL 19
> +#define AUD_CLKID_MST_B_MCLK_DIV 20
> +#define AUD_CLKID_MST_B_MCLK 21
> +#define AUD_CLKID_MST_C_MCLK_SEL 22
> +#define AUD_CLKID_MST_C_MCLK_DIV 23
> +#define AUD_CLKID_MST_C_MCLK 24
> +#define AUD_CLKID_MST_D_MCLK_SEL 25
> +#define AUD_CLKID_MST_D_MCLK_DIV 26
> +#define AUD_CLKID_MST_D_MCLK 27
> +#define AUD_CLKID_SPDIFIN_CLK_SEL 28
> +#define AUD_CLKID_SPDIFIN_CLK_DIV 29
> +#define AUD_CLKID_SPDIFIN_CLK 30
> +#define AUD_CLKID_RESAMPLE_CLK_SEL 31
> +#define AUD_CLKID_RESAMPLE_CLK_DIV 32
> +#define AUD_CLKID_RESAMPLE_CLK 33
> +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
> +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
> +#define AUD_CLKID_LOCKER_IN_CLK 36
> +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
> +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
> +#define AUD_CLKID_LOCKER_OUT_CLK 39
> +#define AUD_CLKID_EQDRC_CLK_SEL 40
> +#define AUD_CLKID_EQDRC_CLK_DIV 41
> +#define AUD_CLKID_EQDRC_CLK 42
> +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
> +#define AUD_CLKID_MST_A_SCLK_DIV 44
> +#define AUD_CLKID_MST_A_SCLK_POST_EN 45
> +#define AUD_CLKID_MST_A_SCLK 46
> +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
> +#define AUD_CLKID_MST_B_SCLK_DIV 48
> +#define AUD_CLKID_MST_B_SCLK_POST_EN 49
> +#define AUD_CLKID_MST_B_SCLK 50
> +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
> +#define AUD_CLKID_MST_C_SCLK_DIV 52
> +#define AUD_CLKID_MST_C_SCLK_POST_EN 53
> +#define AUD_CLKID_MST_C_SCLK 54
> +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
> +#define AUD_CLKID_MST_D_SCLK_DIV 56
> +#define AUD_CLKID_MST_D_SCLK_POST_EN 57
> +#define AUD_CLKID_MST_D_SCLK 58
> +#define AUD_CLKID_MST_A_LRCLK_DIV 59
> +#define AUD_CLKID_MST_A_LRCLK 60
> +#define AUD_CLKID_MST_B_LRCLK_DIV 61
> +#define AUD_CLKID_MST_B_LRCLK 62
> +#define AUD_CLKID_MST_C_LRCLK_DIV 63
> +#define AUD_CLKID_MST_C_LRCLK 64
> +#define AUD_CLKID_MST_D_LRCLK_DIV 65
> +#define AUD_CLKID_MST_D_LRCLK 66
> +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
> +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
> +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
> +#define AUD_CLKID_TDMIN_A_SCLK 70
> +#define AUD_CLKID_TDMIN_A_LRCLK 71
> +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
> +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
> +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
> +#define AUD_CLKID_TDMIN_B_SCLK 75
> +#define AUD_CLKID_TDMIN_B_LRCLK 76
> +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
> +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
> +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
> +#define AUD_CLKID_TDMIN_LB_SCLK 80
> +#define AUD_CLKID_TDMIN_LB_LRCLK 81
> +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
> +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
> +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
> +#define AUD_CLKID_TDMOUT_A_SCLK 85
> +#define AUD_CLKID_TDMOUT_A_LRCLK 86
> +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
> +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
> +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
> +#define AUD_CLKID_TDMOUT_B_SCLK 90
> +#define AUD_CLKID_TDMOUT_B_LRCLK 91
> +
> +#define AUD2_CLKID_DDR_ARB 1
> +#define AUD2_CLKID_PDM 2
> +#define AUD2_CLKID_TDMIN_VAD 3
> +#define AUD2_CLKID_TODDR_VAD 4
> +#define AUD2_CLKID_VAD 5
> +#define AUD2_CLKID_AUDIOTOP 6
> +#define AUD2_CLKID_VAD_MCLK_SEL 7
> +#define AUD2_CLKID_VAD_MCLK_DIV 8
> +#define AUD2_CLKID_VAD_MCLK 9
> +#define AUD2_CLKID_VAD_CLK_SEL 10
> +#define AUD2_CLKID_VAD_CLK_DIV 11
> +#define AUD2_CLKID_VAD_CLK 12
> +#define AUD2_CLKID_PDM_DCLK_SEL 13
> +#define AUD2_CLKID_PDM_DCLK_DIV 14
> +#define AUD2_CLKID_PDM_DCLK 15
> +#define AUD2_CLKID_PDM_SYSCLK_SEL 16
> +#define AUD2_CLKID_PDM_SYSCLK_DIV 17
> +#define AUD2_CLKID_PDM_SYSCLK 18
> +
> +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
> diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
> new file mode 100644
> index 000000000000..653fddba1d8f
> --- /dev/null
> +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + *
> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
> +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
> +
> +#define AUD_RESET_DDRARB 0
> +#define AUD_RESET_TDMIN_A 1
> +#define AUD_RESET_TDMIN_B 2
> +#define AUD_RESET_TDMIN_LB 3
> +#define AUD_RESET_LOOPBACK 4
> +#define AUD_RESET_TDMOUT_A 5
> +#define AUD_RESET_TDMOUT_B 6
> +#define AUD_RESET_FRDDR_A 7
> +#define AUD_RESET_FRDDR_B 8
> +#define AUD_RESET_TODDR_A 9
> +#define AUD_RESET_TODDR_B 10
> +#define AUD_RESET_SPDIFIN 11
> +#define AUD_RESET_RESAMPLE 12
> +#define AUD_RESET_EQDRC 13
> +#define AUD_RESET_LOCKER 14
> +#define AUD_RESET_TOACODEC 30
> +#define AUD_RESET_CLKTREE 31
> +
> +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */


--
Jerome
Re: [RFC PATCH v2 3/5] dt-bindings: clock: meson: document A1 SoC audio clock controller driver [ In reply to ]
jan.dakinevich at salutedevices
Mar 30, 2024, 12:42 PM
Post #6 of 6 (22 views)
Permalink
On 3/29/24 15:24, Jerome Brunet wrote:
>
> On Thu 28 Mar 2024 at 04:08, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>
>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>
>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> ---
>> .../bindings/clock/amlogic,a1-audio-clkc.yaml | 141 ++++++++++++++++++
>> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 +++++++++++++++
>> .../reset/amlogic,meson-a1-audio-reset.h | 29 ++++
>> 3 files changed, 292 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
>> new file mode 100644
>> index 000000000000..1c9ef3292f3c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml
>> @@ -0,0 +1,141 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,a1-audio-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic A1 Audio Clock Control Unit and Reset Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <neil.armstrong@linaro.org>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + - amlogic,a1-audio2-clkc
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 6
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 6
>> + maxItems: 7
>> +
>> +required:
>> + - compatible
>> + - '#clock-cells'
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - amlogic,a1-audio-clkc
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input core clock
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clocks-names:
>> + items:
>> + - const: core
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>> + required:
>> + - '#reset-cells'
>> + else:
>> + properties:
>> + clocks:
>> + items:
>> + - description: input main peripheral bus clock
>> + - description: input dds_in
>> + - description: input fixed pll div2
>> + - description: input fixed pll div3
>> + - description: input hifi_pll
>> + - description: input oscillator (usually at 24MHz)
>> + clock-names:
>> + items:
>> + - const: pclk
>> + - const: dds_in
>> + - const: fclk_div2
>> + - const: fclk_div3
>> + - const: hifi_pll
>> + - const: xtal
>
> All the optional slave clock inputs are missing from this dcoumentation..
> They need to be documentated as well
>
Hmmm... here should be a list of 26 entries. First 6 of them are
mandatory, other are optional.

I have no ideas left on how to describe it in yaml, also I can't find
something similar beside existing schemas... Maybe you can give some advice.

>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
>> + #include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>> + audio {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clkc_audio: audio-clock-controller@fe050000 {
>> + compatible = "amlogic,a1-audio-clkc";
>> + reg = <0x0 0xfe050000 0x0 0xb0>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + clocks = <&clkc_audio2 AUD2_CLKID_AUDIOTOP>,
>> + <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "core",
>> + "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> +
>> + clkc_audio2: audio-clock-controller@fe054800 {
>> + compatible = "amlogic,a1-audio2-clkc";
>> + reg = <0x0 0xfe054800 0x0 0x20>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_periphs CLKID_AUDIO>,
>> + <&clkc_periphs CLKID_DDS_IN>,
>> + <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "pclk",
>> + "dds_in",
>> + "fclk_div2",
>> + "fclk_div3",
>> + "hifi_pll",
>> + "xtal";
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> new file mode 100644
>> index 000000000000..b30df3b1ae08
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h
>> @@ -0,0 +1,122 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H
>> +#define __A1_AUDIO_CLKC_BINDINGS_H
>> +
>> +#define AUD_CLKID_DDR_ARB 1
>> +#define AUD_CLKID_TDMIN_A 2
>> +#define AUD_CLKID_TDMIN_B 3
>> +#define AUD_CLKID_TDMIN_LB 4
>> +#define AUD_CLKID_LOOPBACK 5
>> +#define AUD_CLKID_TDMOUT_A 6
>> +#define AUD_CLKID_TDMOUT_B 7
>> +#define AUD_CLKID_FRDDR_A 8
>> +#define AUD_CLKID_FRDDR_B 9
>> +#define AUD_CLKID_TODDR_A 10
>> +#define AUD_CLKID_TODDR_B 11
>> +#define AUD_CLKID_SPDIFIN 12
>> +#define AUD_CLKID_RESAMPLE 13
>> +#define AUD_CLKID_EQDRC 14
>> +#define AUD_CLKID_LOCKER 15
>> +#define AUD_CLKID_MST_A_MCLK_SEL 16
>> +#define AUD_CLKID_MST_A_MCLK_DIV 17
>> +#define AUD_CLKID_MST_A_MCLK 18
>> +#define AUD_CLKID_MST_B_MCLK_SEL 19
>> +#define AUD_CLKID_MST_B_MCLK_DIV 20
>> +#define AUD_CLKID_MST_B_MCLK 21
>> +#define AUD_CLKID_MST_C_MCLK_SEL 22
>> +#define AUD_CLKID_MST_C_MCLK_DIV 23
>> +#define AUD_CLKID_MST_C_MCLK 24
>> +#define AUD_CLKID_MST_D_MCLK_SEL 25
>> +#define AUD_CLKID_MST_D_MCLK_DIV 26
>> +#define AUD_CLKID_MST_D_MCLK 27
>> +#define AUD_CLKID_SPDIFIN_CLK_SEL 28
>> +#define AUD_CLKID_SPDIFIN_CLK_DIV 29
>> +#define AUD_CLKID_SPDIFIN_CLK 30
>> +#define AUD_CLKID_RESAMPLE_CLK_SEL 31
>> +#define AUD_CLKID_RESAMPLE_CLK_DIV 32
>> +#define AUD_CLKID_RESAMPLE_CLK 33
>> +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34
>> +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35
>> +#define AUD_CLKID_LOCKER_IN_CLK 36
>> +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37
>> +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38
>> +#define AUD_CLKID_LOCKER_OUT_CLK 39
>> +#define AUD_CLKID_EQDRC_CLK_SEL 40
>> +#define AUD_CLKID_EQDRC_CLK_DIV 41
>> +#define AUD_CLKID_EQDRC_CLK 42
>> +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43
>> +#define AUD_CLKID_MST_A_SCLK_DIV 44
>> +#define AUD_CLKID_MST_A_SCLK_POST_EN 45
>> +#define AUD_CLKID_MST_A_SCLK 46
>> +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47
>> +#define AUD_CLKID_MST_B_SCLK_DIV 48
>> +#define AUD_CLKID_MST_B_SCLK_POST_EN 49
>> +#define AUD_CLKID_MST_B_SCLK 50
>> +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51
>> +#define AUD_CLKID_MST_C_SCLK_DIV 52
>> +#define AUD_CLKID_MST_C_SCLK_POST_EN 53
>> +#define AUD_CLKID_MST_C_SCLK 54
>> +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55
>> +#define AUD_CLKID_MST_D_SCLK_DIV 56
>> +#define AUD_CLKID_MST_D_SCLK_POST_EN 57
>> +#define AUD_CLKID_MST_D_SCLK 58
>> +#define AUD_CLKID_MST_A_LRCLK_DIV 59
>> +#define AUD_CLKID_MST_A_LRCLK 60
>> +#define AUD_CLKID_MST_B_LRCLK_DIV 61
>> +#define AUD_CLKID_MST_B_LRCLK 62
>> +#define AUD_CLKID_MST_C_LRCLK_DIV 63
>> +#define AUD_CLKID_MST_C_LRCLK 64
>> +#define AUD_CLKID_MST_D_LRCLK_DIV 65
>> +#define AUD_CLKID_MST_D_LRCLK 66
>> +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67
>> +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68
>> +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69
>> +#define AUD_CLKID_TDMIN_A_SCLK 70
>> +#define AUD_CLKID_TDMIN_A_LRCLK 71
>> +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72
>> +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73
>> +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74
>> +#define AUD_CLKID_TDMIN_B_SCLK 75
>> +#define AUD_CLKID_TDMIN_B_LRCLK 76
>> +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77
>> +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78
>> +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79
>> +#define AUD_CLKID_TDMIN_LB_SCLK 80
>> +#define AUD_CLKID_TDMIN_LB_LRCLK 81
>> +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82
>> +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83
>> +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84
>> +#define AUD_CLKID_TDMOUT_A_SCLK 85
>> +#define AUD_CLKID_TDMOUT_A_LRCLK 86
>> +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87
>> +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88
>> +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89
>> +#define AUD_CLKID_TDMOUT_B_SCLK 90
>> +#define AUD_CLKID_TDMOUT_B_LRCLK 91
>> +
>> +#define AUD2_CLKID_DDR_ARB 1
>> +#define AUD2_CLKID_PDM 2
>> +#define AUD2_CLKID_TDMIN_VAD 3
>> +#define AUD2_CLKID_TODDR_VAD 4
>> +#define AUD2_CLKID_VAD 5
>> +#define AUD2_CLKID_AUDIOTOP 6
>> +#define AUD2_CLKID_VAD_MCLK_SEL 7
>> +#define AUD2_CLKID_VAD_MCLK_DIV 8
>> +#define AUD2_CLKID_VAD_MCLK 9
>> +#define AUD2_CLKID_VAD_CLK_SEL 10
>> +#define AUD2_CLKID_VAD_CLK_DIV 11
>> +#define AUD2_CLKID_VAD_CLK 12
>> +#define AUD2_CLKID_PDM_DCLK_SEL 13
>> +#define AUD2_CLKID_PDM_DCLK_DIV 14
>> +#define AUD2_CLKID_PDM_DCLK 15
>> +#define AUD2_CLKID_PDM_SYSCLK_SEL 16
>> +#define AUD2_CLKID_PDM_SYSCLK_DIV 17
>> +#define AUD2_CLKID_PDM_SYSCLK 18
>> +
>> +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
>> diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
>> new file mode 100644
>> index 000000000000..653fddba1d8f
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
>> @@ -0,0 +1,29 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>> +/*
>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>> + *
>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
>> +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
>> +
>> +#define AUD_RESET_DDRARB 0
>> +#define AUD_RESET_TDMIN_A 1
>> +#define AUD_RESET_TDMIN_B 2
>> +#define AUD_RESET_TDMIN_LB 3
>> +#define AUD_RESET_LOOPBACK 4
>> +#define AUD_RESET_TDMOUT_A 5
>> +#define AUD_RESET_TDMOUT_B 6
>> +#define AUD_RESET_FRDDR_A 7
>> +#define AUD_RESET_FRDDR_B 8
>> +#define AUD_RESET_TODDR_A 9
>> +#define AUD_RESET_TODDR_B 10
>> +#define AUD_RESET_SPDIFIN 11
>> +#define AUD_RESET_RESAMPLE 12
>> +#define AUD_RESET_EQDRC 13
>> +#define AUD_RESET_LOCKER 14
>> +#define AUD_RESET_TOACODEC 30
>> +#define AUD_RESET_CLKTREE 31
>> +
>> +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
>
>

--
Best regards
Jan Dakinevich

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