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Recursion in cpu_physical_memory_rw
Hi:

A number of qemu driver backends (such as rtl8139) call the function
cpu_physical_memory_rw to read/write guest memory. The target guest
memory address is often supplied by the guest. This opens up the
possibility of a guest giving an address which happens to be an MMIO
address which can potentially lead to infinite recursion involving
cpu_physical_memory_rw.

Since these driver backends really only need to access system memory,
we could simply provide a new access interface that does not allow
MMIO addresses.

Any comments on this problem?

Cheers,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
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RE: Recursion in cpu_physical_memory_rw [ In reply to ]
>
>A number of qemu driver backends (such as rtl8139) call the function
>cpu_physical_memory_rw to read/write guest memory. The target guest
>memory address is often supplied by the guest. This opens up the
>possibility of a guest giving an address which happens to be an MMIO
>address which can potentially lead to infinite recursion involving
>cpu_physical_memory_rw.
>
>Since these driver backends really only need to access system memory,
>we could simply provide a new access interface that does not allow
>MMIO addresses.
>
>Any comments on this problem?
>

The interface called paddr_is_ram should help.
-Xin

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Re: [Qemu-devel] Recursion in cpu_physical_memory_rw [ In reply to ]
On Wednesday 15 November 2006 00:43, Herbert Xu wrote:
> Hi:
>
> A number of qemu driver backends (such as rtl8139) call the function
> cpu_physical_memory_rw to read/write guest memory. The target guest
> memory address is often supplied by the guest. This opens up the
> possibility of a guest giving an address which happens to be an MMIO
> address which can potentially lead to infinite recursion involving
> cpu_physical_memory_rw.
>
> Since these driver backends really only need to access system memory,
> we could simply provide a new access interface that does not allow
> MMIO addresses.

It isn't always system memory. Some DMA controllers deliberately write to
device FIFOs. There are also several devices which map areas of onboard RAM.
At minimum you need to make those to use RAM mappings rather than MMIO.

If a device is recursively writing to itself I'd take this as sign that the
guest OS is already pretty screwed. I'm not sure what happens in this
situation on real hardware, but I wouldn't be surprised if it caused similar
effects by flooding the bus.

Paul

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