Mailing List Archive

[PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923
On the Cortex A55, TLB entries can be allocated by a speculative AT
instruction. If this is happening during a guest context switch with an
inconsistent page table state in the guest, TLBs with wrong values might
be allocated.
The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
1165522 on Cortex A76 or Neoverse N1.

This change is also introducing the MIDR identifier for the Cortex-A55.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
docs/misc/arm/silicon-errata.txt | 1 +
xen/arch/arm/cpuerrata.c | 6 ++++++
xen/include/asm-arm/processor.h | 2 ++
3 files changed, 9 insertions(+)

diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
index d183ba543f..27bf957ebf 100644
--- a/docs/misc/arm/silicon-errata.txt
+++ b/docs/misc/arm/silicon-errata.txt
@@ -45,6 +45,7 @@ stable hypervisors.
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
+| ARM | Cortex-A55 | #1530923 | N/A |
| ARM | Cortex-A57 | #852523 | N/A |
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index cb4795beec..b398d480f1 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -514,6 +514,12 @@ static const struct arm_cpu_capabilities arm_errata[] = {
.capability = ARM64_WORKAROUND_AT_SPECULATE,
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
},
+ {
+ /* Cortex-A55 (All versions as erratum is open in SDEN v14) */
+ .desc = "ARM erratum 1530923",
+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
+ },
{},
};

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index d3d12a9d19..87c8136022 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -53,6 +53,7 @@
#define ARM_CPU_PART_CORTEX_A17 0xC0E
#define ARM_CPU_PART_CORTEX_A15 0xC0F
#define ARM_CPU_PART_CORTEX_A53 0xD03
+#define ARM_CPU_PART_CORTEX_A55 0xD05
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define ARM_CPU_PART_CORTEX_A72 0xD08
#define ARM_CPU_PART_CORTEX_A73 0xD09
@@ -64,6 +65,7 @@
#define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17)
#define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15)
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
+#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
--
2.17.1
Re: [PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923 [ In reply to ]
Hello ,

> On 24 Nov 2020, at 11:12 am, Bertrand Marquis <Bertrand.Marquis@arm.com> wrote:
>
> On the Cortex A55, TLB entries can be allocated by a speculative AT
> instruction. If this is happening during a guest context switch with an
> inconsistent page table state in the guest, TLBs with wrong values might
> be allocated.
> The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
> 1165522 on Cortex A76 or Neoverse N1.
>
> This change is also introducing the MIDR identifier for the Cortex-A55.
>
> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>

Reviewed-by: Rahul Singh <rahul.singh@arm.com>

Regards,
Rahul
> ---
> docs/misc/arm/silicon-errata.txt | 1 +
> xen/arch/arm/cpuerrata.c | 6 ++++++
> xen/include/asm-arm/processor.h | 2 ++
> 3 files changed, 9 insertions(+)
>
> diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
> index d183ba543f..27bf957ebf 100644
> --- a/docs/misc/arm/silicon-errata.txt
> +++ b/docs/misc/arm/silicon-errata.txt
> @@ -45,6 +45,7 @@ stable hypervisors.
> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
> | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
> | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
> +| ARM | Cortex-A55 | #1530923 | N/A |
> | ARM | Cortex-A57 | #852523 | N/A |
> | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
> | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
> diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
> index cb4795beec..b398d480f1 100644
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -514,6 +514,12 @@ static const struct arm_cpu_capabilities arm_errata[] = {
> .capability = ARM64_WORKAROUND_AT_SPECULATE,
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
> },
> + {
> + /* Cortex-A55 (All versions as erratum is open in SDEN v14) */
> + .desc = "ARM erratum 1530923",
> + .capability = ARM64_WORKAROUND_AT_SPECULATE,
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> + },
> {},
> };
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index d3d12a9d19..87c8136022 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -53,6 +53,7 @@
> #define ARM_CPU_PART_CORTEX_A17 0xC0E
> #define ARM_CPU_PART_CORTEX_A15 0xC0F
> #define ARM_CPU_PART_CORTEX_A53 0xD03
> +#define ARM_CPU_PART_CORTEX_A55 0xD05
> #define ARM_CPU_PART_CORTEX_A57 0xD07
> #define ARM_CPU_PART_CORTEX_A72 0xD08
> #define ARM_CPU_PART_CORTEX_A73 0xD09
> @@ -64,6 +65,7 @@
> #define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17)
> #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15)
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> +#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
> --
> 2.17.1
>
>
Re: [PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923 [ In reply to ]
On Tue, 24 Nov 2020, Rahul Singh wrote:
> > On 24 Nov 2020, at 11:12 am, Bertrand Marquis <Bertrand.Marquis@arm.com> wrote:
> >
> > On the Cortex A55, TLB entries can be allocated by a speculative AT
> > instruction. If this is happening during a guest context switch with an
> > inconsistent page table state in the guest, TLBs with wrong values might
> > be allocated.
> > The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
> > 1165522 on Cortex A76 or Neoverse N1.
> >
> > This change is also introducing the MIDR identifier for the Cortex-A55.
> >
> > Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
>
> Reviewed-by: Rahul Singh <rahul.singh@arm.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>


> > docs/misc/arm/silicon-errata.txt | 1 +
> > xen/arch/arm/cpuerrata.c | 6 ++++++
> > xen/include/asm-arm/processor.h | 2 ++
> > 3 files changed, 9 insertions(+)
> >
> > diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
> > index d183ba543f..27bf957ebf 100644
> > --- a/docs/misc/arm/silicon-errata.txt
> > +++ b/docs/misc/arm/silicon-errata.txt
> > @@ -45,6 +45,7 @@ stable hypervisors.
> > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
> > | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
> > | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
> > +| ARM | Cortex-A55 | #1530923 | N/A |
> > | ARM | Cortex-A57 | #852523 | N/A |
> > | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
> > | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
> > diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
> > index cb4795beec..b398d480f1 100644
> > --- a/xen/arch/arm/cpuerrata.c
> > +++ b/xen/arch/arm/cpuerrata.c
> > @@ -514,6 +514,12 @@ static const struct arm_cpu_capabilities arm_errata[] = {
> > .capability = ARM64_WORKAROUND_AT_SPECULATE,
> > MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
> > },
> > + {
> > + /* Cortex-A55 (All versions as erratum is open in SDEN v14) */
> > + .desc = "ARM erratum 1530923",
> > + .capability = ARM64_WORKAROUND_AT_SPECULATE,
> > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> > + },
> > {},
> > };
> >
> > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> > index d3d12a9d19..87c8136022 100644
> > --- a/xen/include/asm-arm/processor.h
> > +++ b/xen/include/asm-arm/processor.h
> > @@ -53,6 +53,7 @@
> > #define ARM_CPU_PART_CORTEX_A17 0xC0E
> > #define ARM_CPU_PART_CORTEX_A15 0xC0F
> > #define ARM_CPU_PART_CORTEX_A53 0xD03
> > +#define ARM_CPU_PART_CORTEX_A55 0xD05
> > #define ARM_CPU_PART_CORTEX_A57 0xD07
> > #define ARM_CPU_PART_CORTEX_A72 0xD08
> > #define ARM_CPU_PART_CORTEX_A73 0xD09
> > @@ -64,6 +65,7 @@
> > #define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17)
> > #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15)
> > #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> > +#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
> > #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> > #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> > #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
> > --
> > 2.17.1
> >
> >
>
Re: [PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923 [ In reply to ]
On 24/11/2020 17:44, Stefano Stabellini wrote:
> On Tue, 24 Nov 2020, Rahul Singh wrote:
>>> On 24 Nov 2020, at 11:12 am, Bertrand Marquis <Bertrand.Marquis@arm.com> wrote:
>>>
>>> On the Cortex A55, TLB entries can be allocated by a speculative AT
>>> instruction. If this is happening during a guest context switch with an
>>> inconsistent page table state in the guest, TLBs with wrong values might
>>> be allocated.
>>> The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
>>> 1165522 on Cortex A76 or Neoverse N1.
>>>
>>> This change is also introducing the MIDR identifier for the Cortex-A55.
>>>
>>> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
>>
>> Reviewed-by: Rahul Singh <rahul.singh@arm.com>
>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

Acked-by: Julien Grall <jgrall@amazon.com>

And committed.

Cheers,

--
Julien Grall
Re: [PATCH] xen/arm: Add workaround for Cortex-A55 erratum #1530923 [ In reply to ]
> On 25 Nov 2020, at 11:26, Julien Grall <julien@xen.org> wrote:
>
>
>
> On 24/11/2020 17:44, Stefano Stabellini wrote:
>> On Tue, 24 Nov 2020, Rahul Singh wrote:
>>>> On 24 Nov 2020, at 11:12 am, Bertrand Marquis <Bertrand.Marquis@arm.com> wrote:
>>>>
>>>> On the Cortex A55, TLB entries can be allocated by a speculative AT
>>>> instruction. If this is happening during a guest context switch with an
>>>> inconsistent page table state in the guest, TLBs with wrong values might
>>>> be allocated.
>>>> The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
>>>> 1165522 on Cortex A76 or Neoverse N1.
>>>>
>>>> This change is also introducing the MIDR identifier for the Cortex-A55.
>>>>
>>>> Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
>>>
>>> Reviewed-by: Rahul Singh <rahul.singh@arm.com>
>> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
>
> Acked-by: Julien Grall <jgrall@amazon.com>
>
> And committed.

Thanks :-)

Cheers
Bertrand

>
> Cheers,
>
> --
> Julien Grall