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[xen master] xen/riscv: add <asm/csr.h> header
commit bd960d612840f7204911e592734a87bcd3193166
Author: Oleksii Kurochko <oleksii.kurochko@gmail.com>
AuthorDate: Thu Feb 9 11:15:08 2023 +0100
Commit: Jan Beulich <jbeulich@suse.com>
CommitDate: Thu Feb 9 11:15:08 2023 +0100

xen/riscv: add <asm/csr.h> header

The following changes were made in comparison with <asm/csr.h> from
Linux:
* remove all defines as they are defined in riscv_encoding.h
* leave only csr_* macros

Origin: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ d2d11f342b17
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
xen/arch/riscv/include/asm/csr.h | 84 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)

diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h
new file mode 100644
index 0000000000..8215562343
--- /dev/null
+++ b/xen/arch/riscv/include/asm/csr.h
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_CSR_H
+#define _ASM_RISCV_CSR_H
+
+#include <asm/asm.h>
+#include <xen/const.h>
+#include <asm/riscv_encoding.h>
+
+#ifndef __ASSEMBLY__
+
+#define csr_read(csr) \
+({ \
+ register unsigned long __v; \
+ __asm__ __volatile__ ( "csrr %0, " __ASM_STR(csr) \
+ : "=r" (__v) \
+ : : "memory" ); \
+ __v; \
+})
+
+#define csr_write(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrw " __ASM_STR(csr) ", %0" \
+ : /* no outputs */ \
+ : "rK" (__v) \
+ : "memory" ); \
+})
+
+#define csr_swap(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrrw %0, " __ASM_STR(csr) ", %1" \
+ : "=r" (__v) \
+ : "rK" (__v) \
+ : "memory" ); \
+ __v; \
+})
+
+#define csr_read_set(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrrs %0, " __ASM_STR(csr) ", %1" \
+ : "=r" (__v) \
+ : "rK" (__v) \
+ : "memory" ); \
+ __v; \
+})
+
+#define csr_set(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrs " __ASM_STR(csr) ", %0" \
+ : /* no outputs */ \
+ : "rK" (__v) \
+ : "memory" ); \
+})
+
+#define csr_read_clear(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrrc %0, " __ASM_STR(csr) ", %1" \
+ : "=r" (__v) \
+ : "rK" (__v) \
+ : "memory" ); \
+ __v; \
+})
+
+#define csr_clear(csr, val) \
+({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__ ( "csrc " __ASM_STR(csr) ", %0" \
+ : /* no outputs */ \
+ : "rK" (__v) \
+ : "memory" ); \
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_CSR_H */
--
generated by git-patchbot for /home/xen/git/xen.git#master