Mailing List Archive

[xen staging] x86/CPUID: add further "fast repeated string ops" feature flags
commit a8c532be6a44c7faa54ac777a717f4aa65e3a806
Author: Jan Beulich <jbeulich@suse.com>
AuthorDate: Mon Apr 19 15:29:39 2021 +0200
Commit: Jan Beulich <jbeulich@suse.com>
CommitDate: Mon Apr 19 15:29:39 2021 +0200

x86/CPUID: add further "fast repeated string ops" feature flags

Like ERMS this can always be exposed to guests, but I guess once we
introduce full validation we want to make sure we don't reject incoming
policies with any of these set when in the raw/host policies they're
clear.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
tools/libs/light/libxl_cpuid.c | 4 ++++
tools/misc/xen-cpuid.c | 3 +++
xen/include/public/arch-x86/cpufeatureset.h | 4 ++++
3 files changed, 11 insertions(+)

diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index aee28b0430..943a343239 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -215,6 +215,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)

{"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
{"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
+ {"fsrm", 0x00000007, 0, CPUID_REG_EDX, 4, 1},
{"avx512-vp2intersect",0x00000007,0,CPUID_REG_EDX,8, 1},
{"srbds-ctrl", 0x00000007, 0, CPUID_REG_EDX, 9, 1},
{"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1},
@@ -229,6 +230,9 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)

{"avx-vnni", 0x00000007, 1, CPUID_REG_EAX, 4, 1},
{"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1},
+ {"fzrm", 0x00000007, 1, CPUID_REG_EAX, 10, 1},
+ {"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1},
+ {"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1},

{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
{"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 628e8f5aa2..b4229d1126 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -177,6 +177,9 @@ static const char *const str_7d0[32] =
static const char *const str_7a1[32] =
{
[ 4] = "avx-vnni", [ 5] = "avx512-bf16",
+
+ [10] = "fzrm", [11] = "fsrs",
+ [12] = "fsrcs",
};

static const struct {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 42bc8d4279..7cdd08d551 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -261,6 +261,7 @@ XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
+XEN_CPUFEATURE(FSRM, 9*32+ 4) /*A Fast Short REP MOVS */
XEN_CPUFEATURE(AVX512_VP2INTERSECT, 9*32+8) /*a VP2INTERSECT{D,Q} insns */
XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */
XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */
@@ -277,6 +278,9 @@ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */
XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */
+XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */
+XEN_CPUFEATURE(FSRS, 10*32+11) /*A Fast Short REP STOSB */
+XEN_CPUFEATURE(FSRCS, 10*32+12) /*A Fast Short REP CMPSB/SCASB */

#endif /* XEN_CPUFEATURE */

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