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commit e8adbf680b56a3f4b9600c7bcc04fec1877a6213
Author: Wei Chen <wei.chen@arm.com>
AuthorDate: Fri Jan 8 14:29:53 2021 +0800
Commit: Julien Grall <jgrall@amazon.com>
CommitDate: Wed Jan 20 17:55:27 2021 +0000

xen/arm: Don't ignore the affinity level 3 in the MPIDR

Currently, Xen is considering that all the affinity bits are defined
below 32-bit. However, Arm64 define a 3rd level affinity in bits 32-39.

The function gicv3_send_sgi_list in the GICv3 driver will compute the
cluster using the following code:

uint64_t cluster_id = cpu_logical_map(cpu) & ~MPIDR_AFF0_MASK;

Because MPIDR_AFF0_MASK is defined as a 32-bit value, we will miss out
the 3rd level affinity. As a consequence, the IPI would not be sent to
the correct vCPU.

This particular error can be solved by switching MPIDR_AFF0_MASK to use
unsigned long. However, take the opportunity to switch all the MPIDR_*
define to use unsigned long to avoid anymore issue.

Signed-off-by: Wei Chen <wei.chen@arm.com>
[julien: Reword the commit message]
Reviewed-by: Julien Grall <jgrall@amazon.com>
---
xen/include/asm-arm/processor.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 87c8136022..5c1768cdec 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -75,11 +75,11 @@

/* MPIDR Multiprocessor Affinity Register */
#define _MPIDR_UP (30)
-#define MPIDR_UP (_AC(1,U) << _MPIDR_UP)
+#define MPIDR_UP (_AC(1,UL) << _MPIDR_UP)
#define _MPIDR_SMP (31)
-#define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP)
+#define MPIDR_SMP (_AC(1,UL) << _MPIDR_SMP)
#define MPIDR_AFF0_SHIFT (0)
-#define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
+#define MPIDR_AFF0_MASK (_AC(0xff,UL) << MPIDR_AFF0_SHIFT)
#ifdef CONFIG_ARM_64
#define MPIDR_HWID_MASK _AC(0xff00ffffff,UL)
#else
--
generated by git-patchbot for /home/xen/git/xen.git#staging