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Linus,

please pull the latest timers-core-for-linus git tree from:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers-core-for-linus

The time(r) core and clockevent updates are mostly boring this time:

- A new driver for the Tegra210 timer

- Small fixes and improvements alll over the place

- Documentation updates and cleanups

Thanks,

tglx

------------------>
Anson Huang (1):
dt-bindings: timer: gpt: update binding doc

Atish Patra (1):
clocksource/drivers/riscv: Add required checks during clock source init

Biju Das (2):
dt-bindings: timer: renesas, cmt: Document r8a774c0 CMT support
dt-bindings: timer: renesas: tmu: Document r8a774c0 bindings

Chen-Yu Tsai (1):
clocksource/drivers/sun5i: Fail gracefully when clock rate is unavailable

Daniel Lezcano (3):
clocksource/drivers/tango-xtal: Rename the file for consistency
clocksource/drivers/timer-pxa: Rename the file for consistency
clocksource/drivers/timer-cs5535: Rename the file for consistency

Greg Kroah-Hartman (1):
timekeeping/debug: No need to check return value of debugfs_create functions

Gustavo A. R. Silva (1):
timers: Mark expected switch fall-throughs

Joseph Lo (3):
dt-bindings: timer: add Tegra210 timer
clocksource/drivers/tegra: Add Tegra210 timer support
soc/tegra: default select TEGRA_TIMER for Tegra210

Krzysztof Kozlowski (1):
clocksource/drivers/exynos_mct: Remove unused header includes

Marek Szyprowski (2):
clocksource/drivers/exynos_mct: Remove dead code
clocksource/drivers/exynos_mct: Fix error path in timer resources initialization

Paul E. McKenney (1):
time: Move CONTEXT_TRACKING to kernel/time/Kconfig

Ryder Lee (1):
dt-bindings: timer: mediatek: update bindings for MT7629 SoC

Samuel Holland (1):
clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability

Stuart Menefy (2):
clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISR
clocksource/drivers/exynos_mct: Clear timer interrupt when shutdown

Thomas Gleixner (1):
posix-cpu-timers: Remove private interval storage


Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/timer/fsl,imxgpt.txt | 39 ++-
.../bindings/timer/mediatek,mtk-timer.txt | 11 +-
.../bindings/timer/nvidia,tegra210-timer.txt | 36 ++
.../devicetree/bindings/timer/renesas,cmt.txt | 2 +
.../devicetree/bindings/timer/renesas,tmu.txt | 1 +
drivers/clocksource/Kconfig | 13 +-
drivers/clocksource/Makefile | 6 +-
drivers/clocksource/arm_arch_timer.c | 55 +++
drivers/clocksource/exynos_mct.c | 48 +--
.../{cs5535-clockevt.c => timer-cs5535.c} | 0
drivers/clocksource/{pxa_timer.c => timer-pxa.c} | 0
drivers/clocksource/timer-riscv.c | 23 +-
drivers/clocksource/timer-sun5i.c | 10 +
.../{tango_xtal.c => timer-tango-xtal.c} | 0
drivers/clocksource/timer-tegra20.c | 370 ++++++++++++++-------
drivers/soc/tegra/Kconfig | 1 +
include/linux/cpuhotplug.h | 1 +
include/linux/posix-timers.h | 2 +-
kernel/rcu/Kconfig | 30 --
kernel/time/Kconfig | 29 ++
kernel/time/hrtimer.c | 2 +-
kernel/time/posix-cpu-timers.c | 13 +-
kernel/time/tick-broadcast.c | 1 +
kernel/time/timekeeping_debug.c | 11 +-
kernel/time/timer.c | 2 +-
26 files changed, 511 insertions(+), 197 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
rename drivers/clocksource/{cs5535-clockevt.c => timer-cs5535.c} (100%)
rename drivers/clocksource/{pxa_timer.c => timer-pxa.c} (100%)
rename drivers/clocksource/{tango_xtal.c => timer-tango-xtal.c} (100%)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 1f09d043d086..ddb8ce5333ba 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -44,6 +44,8 @@ stable kernels.

| Implementor | Component | Erratum ID | Kconfig |
+----------------+-----------------+-----------------+-----------------------------+
+| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
+| | | | |
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
index 9809b11f7180..5d8fd5b52598 100644
--- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
@@ -2,17 +2,44 @@ Freescale i.MX General Purpose Timer (GPT)

Required properties:

-- compatible : should be "fsl,<soc>-gpt"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 4 interrupts; one per timer channel.
-- clocks : The clocks provided by the SoC to drive the timer.
+- compatible : should be one of following:
+ for i.MX1:
+ - "fsl,imx1-gpt";
+ for i.MX21:
+ - "fsl,imx21-gpt";
+ for i.MX27:
+ - "fsl,imx27-gpt", "fsl,imx21-gpt";
+ for i.MX31:
+ - "fsl,imx31-gpt";
+ for i.MX25:
+ - "fsl,imx25-gpt", "fsl,imx31-gpt";
+ for i.MX50:
+ - "fsl,imx50-gpt", "fsl,imx31-gpt";
+ for i.MX51:
+ - "fsl,imx51-gpt", "fsl,imx31-gpt";
+ for i.MX53:
+ - "fsl,imx53-gpt", "fsl,imx31-gpt";
+ for i.MX6Q:
+ - "fsl,imx6q-gpt", "fsl,imx31-gpt";
+ for i.MX6DL:
+ - "fsl,imx6dl-gpt";
+ for i.MX6SL:
+ - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
+ for i.MX6SX:
+ - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
+- reg : specifies base physical address and size of the registers.
+- interrupts : should be the gpt interrupt.
+- clocks : the clocks provided by the SoC to drive the timer, must contain
+ an entry for each entry in clock-names.
+- clock-names : must include "ipg" entry first, then "per" entry.

Example:

gpt1: timer@10003000 {
- compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+ compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
reg = <0x10003000 0x1000>;
interrupts = <26>;
- clocks = <&clks 46>, <&clks 61>;
+ clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
+ <&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
};
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 18d4d0166c76..ff7c567a7972 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -1,7 +1,7 @@
-Mediatek Timers
+MediaTek Timers
---------------

-Mediatek SoCs have two different timers on different platforms,
+MediaTek SoCs have two different timers on different platforms,
- GPT (General Purpose Timer)
- SYST (System Timer)

@@ -9,6 +9,7 @@ The proper timer will be selected automatically by driver.

Required properties:
- compatible should contain:
+ For those SoCs that use GPT
* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
@@ -17,7 +18,11 @@ Required properties:
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
- * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)
+
+ For those SoCs that use SYST
+ * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
+ * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
+
- reg: Should contain location and length for timer register.
- clocks: Should contain system clock.

diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
new file mode 100644
index 000000000000..032cda96fe0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra210 timer
+
+The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
+timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
+from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
+(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
+or watchdog interrupts.
+
+Required properties:
+- compatible : "nvidia,tegra210-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 14 interrupts; one per each timer channels 0 through
+ 13.
+- clocks : Must contain one entry, for the module clock.
+ See ../clocks/clock-bindings.txt for details.
+
+timer@60005000 {
+ compatible = "nvidia,tegra210-timer";
+ reg = <0x0 0x60005000 0x0 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+ clock-names = "timer";
+};
diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
index 862a80f0380a..c0594450e9ef 100644
--- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
@@ -32,6 +32,8 @@ Required Properties:
- "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470.
- "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1.
- "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1.
+ - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0.
+ - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0.
- "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
- "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
- "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
index 4ddff85837da..13ad07416bdd 100644
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
@@ -10,6 +10,7 @@ Required Properties:

- compatible: must contain one or more of the following:
- "renesas,tmu-r8a7740" for the r8a7740 TMU
+ - "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- "renesas,tmu-r8a7778" for the r8a7778 TMU
- "renesas,tmu-r8a7779" for the r8a7779 TMU
- "renesas,tmu-r8a77970" for the r8a77970 TMU
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6a81a1..5d93e580e5dc 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,7 +131,8 @@ config SUN5I_HSTIMER
config TEGRA_TIMER
bool "Tegra timer driver" if COMPILE_TEST
select CLKSRC_MMIO
- depends on ARM
+ select TIMER_OF
+ depends on ARM || ARM64
help
Enables support for the Tegra driver.

@@ -360,6 +361,16 @@ config ARM64_ERRATUM_858921
The workaround will be dynamically enabled when an affected
core is detected.

+config SUN50I_ERRATUM_UNKNOWN1
+ bool "Workaround for Allwinner A64 erratum UNKNOWN1"
+ default y
+ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI
+ select ARM_ARCH_TIMER_OOL_WORKAROUND
+ help
+ This option enables a workaround for instability in the timer on
+ the Allwinner A64 SoC. The workaround will only be active if the
+ allwinner,erratum-unknown1 property is found in the timer node.
+
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select TIMER_OF if OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cdd210ff89ea..c4a8e9ef932a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
-obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
+obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
@@ -29,7 +29,7 @@ obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o
obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o
obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o
obj-$(CONFIG_MXS_TIMER) += mxs_timer.o
-obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
+obj-$(CONFIG_CLKSRC_PXA) += timer-pxa.o
obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o
obj-$(CONFIG_U300_TIMER) += timer-u300.o
obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o
@@ -69,7 +69,7 @@ obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o
obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
-obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
+obj-$(CONFIG_CLKSRC_TANGO_XTAL) += timer-tango-xtal.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9a7d4dc00b6e..a8b20b65bd4b 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void)
}
#endif

+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
+/*
+ * The low bits of the counter registers are indeterminate while bit 10 or
+ * greater is rolling over. Since the counter value can jump both backward
+ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
+ * with all ones or all zeros in the low bits. Bound the loop by the maximum
+ * number of CPU cycles in 3 consecutive 24 MHz counter periods.
+ */
+#define __sun50i_a64_read_reg(reg) ({ \
+ u64 _val; \
+ int _retries = 150; \
+ \
+ do { \
+ _val = read_sysreg(reg); \
+ _retries--; \
+ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
+ \
+ WARN_ON_ONCE(!_retries); \
+ _val; \
+})
+
+static u64 notrace sun50i_a64_read_cntpct_el0(void)
+{
+ return __sun50i_a64_read_reg(cntpct_el0);
+}
+
+static u64 notrace sun50i_a64_read_cntvct_el0(void)
+{
+ return __sun50i_a64_read_reg(cntvct_el0);
+}
+
+static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
+{
+ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
+}
+
+static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
+{
+ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
+}
+#endif
+
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
},
#endif
+#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
+ {
+ .match_type = ate_match_dt,
+ .id = "allwinner,erratum-unknown1",
+ .desc = "Allwinner erratum UNKNOWN1",
+ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
+ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
+ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
+ },
+#endif
};

typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 7a244b681876..34bd250d46c6 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -10,14 +10,12 @@
* published by the Free Software Foundation.
*/

-#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
-#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <linux/of.h>
@@ -388,6 +386,13 @@ static void exynos4_mct_tick_start(unsigned long cycles,
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

+static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+{
+ /* Clear the MCT tick interrupt */
+ if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
+ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+}
+
static int exynos4_tick_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
@@ -404,6 +409,7 @@ static int set_state_shutdown(struct clock_event_device *evt)

mevt = container_of(evt, struct mct_clock_event_device, evt);
exynos4_mct_tick_stop(mevt);
+ exynos4_mct_tick_clear(mevt);
return 0;
}

@@ -420,8 +426,11 @@ static int set_state_periodic(struct clock_event_device *evt)
return 0;
}

-static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
+ struct mct_clock_event_device *mevt = dev_id;
+ struct clock_event_device *evt = &mevt->evt;
+
/*
* This is for supporting oneshot mode.
* Mct would generate interrupt periodically
@@ -430,16 +439,6 @@ static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
if (!clockevent_state_periodic(&mevt->evt))
exynos4_mct_tick_stop(mevt);

- /* Clear the MCT tick interrupt */
- if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
- exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
-}
-
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-{
- struct mct_clock_event_device *mevt = dev_id;
- struct clock_event_device *evt = &mevt->evt;
-
exynos4_mct_tick_clear(mevt);

evt->event_handler(evt);
@@ -507,13 +506,12 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem *
int err, cpu;
struct clk *mct_clk, *tick_clk;

- tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
- clk_get(NULL, "fin_pll");
+ tick_clk = of_clk_get_by_name(np, "fin_pll");
if (IS_ERR(tick_clk))
panic("%s: unable to determine tick clock rate\n", __func__);
clk_rate = clk_get_rate(tick_clk);

- mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
+ mct_clk = of_clk_get_by_name(np, "mct");
if (IS_ERR(mct_clk))
panic("%s: unable to retrieve mct clock instance\n", __func__);
clk_prepare_enable(mct_clk);
@@ -562,7 +560,19 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem *
return 0;

out_irq:
- free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
+ if (mct_int_type == MCT_INT_PPI) {
+ free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
+ } else {
+ for_each_possible_cpu(cpu) {
+ struct mct_clock_event_device *pcpu_mevt =
+ per_cpu_ptr(&percpu_mct_tick, cpu);
+
+ if (pcpu_mevt->evt.irq != -1) {
+ free_irq(pcpu_mevt->evt.irq, pcpu_mevt);
+ pcpu_mevt->evt.irq = -1;
+ }
+ }
+ }
return err;
}

@@ -581,11 +591,7 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type)
* timer irqs are specified after the four global timer
* irqs are specified.
*/
-#ifdef CONFIG_OF
nr_irqs = of_irq_count(np);
-#else
- nr_irqs = 0;
-#endif
for (i = MCT_L0_IRQ; i < nr_irqs; i++)
mct_irqs[i] = irq_of_parse_and_map(np, i);

diff --git a/drivers/clocksource/cs5535-clockevt.c b/drivers/clocksource/timer-cs5535.c
similarity index 100%
rename from drivers/clocksource/cs5535-clockevt.c
rename to drivers/clocksource/timer-cs5535.c
diff --git a/drivers/clocksource/pxa_timer.c b/drivers/clocksource/timer-pxa.c
similarity index 100%
rename from drivers/clocksource/pxa_timer.c
rename to drivers/clocksource/timer-pxa.c
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 431892200a08..e8163693e936 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -95,13 +95,30 @@ static int __init riscv_timer_init_dt(struct device_node *n)
struct clocksource *cs;

hartid = riscv_of_processor_hartid(n);
+ if (hartid < 0) {
+ pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
+ n, hartid);
+ return hartid;
+ }
+
cpuid = riscv_hartid_to_cpuid(hartid);
+ if (cpuid < 0) {
+ pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
+ return cpuid;
+ }

if (cpuid != smp_processor_id())
return 0;

+ pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
+ __func__, cpuid, hartid);
cs = per_cpu_ptr(&riscv_clocksource, cpuid);
- clocksource_register_hz(cs, riscv_timebase);
+ error = clocksource_register_hz(cs, riscv_timebase);
+ if (error) {
+ pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
+ error, cpuid);
+ return error;
+ }

sched_clock_register(riscv_sched_clock,
BITS_PER_LONG, riscv_timebase);
@@ -110,8 +127,8 @@ static int __init riscv_timer_init_dt(struct device_node *n)
"clockevents/riscv/timer:starting",
riscv_timer_starting_cpu, riscv_timer_dying_cpu);
if (error)
- pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
- error, cpuid);
+ pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
+ error);
return error;
}

diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index 3b56ea3f52af..552c5254390c 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -202,6 +202,11 @@ static int __init sun5i_setup_clocksource(struct device_node *node,
}

rate = clk_get_rate(clk);
+ if (!rate) {
+ pr_err("Couldn't get parent clock rate\n");
+ ret = -EINVAL;
+ goto err_disable_clk;
+ }

cs->timer.base = base;
cs->timer.clk = clk;
@@ -275,6 +280,11 @@ static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem
}

rate = clk_get_rate(clk);
+ if (!rate) {
+ pr_err("Couldn't get parent clock rate\n");
+ ret = -EINVAL;
+ goto err_disable_clk;
+ }

ce->timer.base = base;
ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
diff --git a/drivers/clocksource/tango_xtal.c b/drivers/clocksource/timer-tango-xtal.c
similarity index 100%
rename from drivers/clocksource/tango_xtal.c
rename to drivers/clocksource/timer-tango-xtal.c
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
index 4293943f4e2b..fdb3d795a409 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -15,21 +15,24 @@
*
*/

-#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
#include <linux/err.h>
-#include <linux/time.h>
#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/percpu.h>
#include <linux/sched_clock.h>
-#include <linux/delay.h>
+#include <linux/time.h>
+
+#include "timer-of.h"

+#ifdef CONFIG_ARM
#include <asm/mach/time.h>
+#endif

#define RTC_SECONDS 0x08
#define RTC_SHADOW_SECONDS 0x0c
@@ -39,74 +42,161 @@
#define TIMERUS_USEC_CFG 0x14
#define TIMERUS_CNTR_FREEZE 0x4c

-#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
+#define TIMER_PTV 0x0
+#define TIMER_PTV_EN BIT(31)
+#define TIMER_PTV_PER BIT(30)
+#define TIMER_PCR 0x4
+#define TIMER_PCR_INTR_CLR BIT(30)
+
+#ifdef CONFIG_ARM
+#define TIMER_CPU0 0x50 /* TIMER3 */
+#else
+#define TIMER_CPU0 0x90 /* TIMER10 */
+#define TIMER10_IRQ_IDX 10
+#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu)
+#endif
+#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+
+static u32 usec_config;
static void __iomem *timer_reg_base;
+#ifdef CONFIG_ARM
static void __iomem *rtc_base;
-
static struct timespec64 persistent_ts;
static u64 persistent_ms, last_persistent_ms;
-
static struct delay_timer tegra_delay_timer;
-
-#define timer_writel(value, reg) \
- writel_relaxed(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
- readl_relaxed(timer_reg_base + (reg))
+#endif

static int tegra_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
- u32 reg;
+ void __iomem *reg_base = timer_of_base(to_timer_of(evt));

- reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
- timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+ writel(TIMER_PTV_EN |
+ ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+ reg_base + TIMER_PTV);

return 0;
}

-static inline void timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_shutdown(struct clock_event_device *evt)
{
- timer_writel(0, TIMER3_BASE + TIMER_PTV);
+ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ writel(0, reg_base + TIMER_PTV);
+
+ return 0;
}

-static int tegra_timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
- timer_shutdown(evt);
+ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ writel(TIMER_PTV_EN | TIMER_PTV_PER |
+ ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+ reg_base + TIMER_PTV);
+
return 0;
}

-static int tegra_timer_set_periodic(struct clock_event_device *evt)
+static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static void tegra_timer_suspend(struct clock_event_device *evt)
+{
+ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+}
+
+static void tegra_timer_resume(struct clock_event_device *evt)
+{
+ writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
+}
+
+#ifdef CONFIG_ARM64
+static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
+ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+ .clkevt = {
+ .name = "tegra_timer",
+ .rating = 460,
+ .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+ .set_next_event = tegra_timer_set_next_event,
+ .set_state_shutdown = tegra_timer_shutdown,
+ .set_state_periodic = tegra_timer_set_periodic,
+ .set_state_oneshot = tegra_timer_shutdown,
+ .tick_resume = tegra_timer_shutdown,
+ .suspend = tegra_timer_suspend,
+ .resume = tegra_timer_resume,
+ },
+};
+
+static int tegra_timer_setup(unsigned int cpu)
{
- u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
+ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+ irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
+ enable_irq(to->clkevt.irq);
+
+ clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+ 1, /* min */
+ 0x1fffffff); /* 29 bits */

- timer_shutdown(evt);
- timer_writel(reg, TIMER3_BASE + TIMER_PTV);
return 0;
}

-static struct clock_event_device tegra_clockevent = {
- .name = "timer0",
- .rating = 300,
- .features = CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_DYNIRQ,
- .set_next_event = tegra_timer_set_next_event,
- .set_state_shutdown = tegra_timer_shutdown,
- .set_state_periodic = tegra_timer_set_periodic,
- .set_state_oneshot = tegra_timer_shutdown,
- .tick_resume = tegra_timer_shutdown,
+static int tegra_timer_stop(unsigned int cpu)
+{
+ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+ to->clkevt.set_state_shutdown(&to->clkevt);
+ disable_irq_nosync(to->clkevt.irq);
+
+ return 0;
+}
+#else /* CONFIG_ARM */
+static struct timer_of tegra_to = {
+ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
+
+ .clkevt = {
+ .name = "tegra_timer",
+ .rating = 300,
+ .features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_DYNIRQ,
+ .set_next_event = tegra_timer_set_next_event,
+ .set_state_shutdown = tegra_timer_shutdown,
+ .set_state_periodic = tegra_timer_set_periodic,
+ .set_state_oneshot = tegra_timer_shutdown,
+ .tick_resume = tegra_timer_shutdown,
+ .suspend = tegra_timer_suspend,
+ .resume = tegra_timer_resume,
+ .cpumask = cpu_possible_mask,
+ },
+
+ .of_irq = {
+ .index = 2,
+ .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
+ .handler = tegra_timer_isr,
+ },
};

static u64 notrace tegra_read_sched_clock(void)
{
- return timer_readl(TIMERUS_CNTR_1US);
+ return readl(timer_reg_base + TIMERUS_CNTR_1US);
+}
+
+static unsigned long tegra_delay_timer_read_counter_long(void)
+{
+ return readl(timer_reg_base + TIMERUS_CNTR_1US);
}

/*
@@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
*ts = persistent_ts;
}
+#endif

-static unsigned long tegra_delay_timer_read_counter_long(void)
-{
- return readl(timer_reg_base + TIMERUS_CNTR_1US);
-}
-
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = (struct clock_event_device *)dev_id;
- timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction tegra_timer_irq = {
- .name = "timer0",
- .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
- .handler = tegra_timer_interrupt,
- .dev_id = &tegra_clockevent,
-};
-
-static int __init tegra20_init_timer(struct device_node *np)
+static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
{
- struct clk *clk;
- unsigned long rate;
- int ret;
-
- timer_reg_base = of_iomap(np, 0);
- if (!timer_reg_base) {
- pr_err("Can't map timer registers\n");
- return -ENXIO;
- }
+ int ret = 0;

- tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
- if (tegra_timer_irq.irq <= 0) {
- pr_err("Failed to map timer IRQ\n");
- return -EINVAL;
- }
+ ret = timer_of_init(np, to);
+ if (ret < 0)
+ goto out;

- clk = of_clk_get(np, 0);
- if (IS_ERR(clk)) {
- pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
- rate = 12000000;
- } else {
- clk_prepare_enable(clk);
- rate = clk_get_rate(clk);
- }
+ timer_reg_base = timer_of_base(to);

- switch (rate) {
+ /*
+ * Configure microsecond timers to have 1MHz clock
+ * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
+ * Uses n+1 scheme
+ */
+ switch (timer_of_rate(to)) {
case 12000000:
- timer_writel(0x000b, TIMERUS_USEC_CFG);
+ usec_config = 0x000b; /* (11+1)/(0+1) */
+ break;
+ case 12800000:
+ usec_config = 0x043f; /* (63+1)/(4+1) */
break;
case 13000000:
- timer_writel(0x000c, TIMERUS_USEC_CFG);
+ usec_config = 0x000c; /* (12+1)/(0+1) */
+ break;
+ case 16800000:
+ usec_config = 0x0453; /* (83+1)/(4+1) */
break;
case 19200000:
- timer_writel(0x045f, TIMERUS_USEC_CFG);
+ usec_config = 0x045f; /* (95+1)/(4+1) */
break;
case 26000000:
- timer_writel(0x0019, TIMERUS_USEC_CFG);
+ usec_config = 0x0019; /* (25+1)/(0+1) */
+ break;
+ case 38400000:
+ usec_config = 0x04bf; /* (191+1)/(4+1) */
+ break;
+ case 48000000:
+ usec_config = 0x002f; /* (47+1)/(0+1) */
break;
default:
- WARN(1, "Unknown clock rate");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
+
+out:
+ return ret;
+}
+
+#ifdef CONFIG_ARM64
+static int __init tegra_init_timer(struct device_node *np)
+{
+ int cpu, ret = 0;
+ struct timer_of *to;
+
+ to = this_cpu_ptr(&tegra_to);
+ ret = tegra_timer_common_init(np, to);
+ if (ret < 0)
+ goto out;
+
+ for_each_possible_cpu(cpu) {
+ struct timer_of *cpu_to;
+
+ cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+ cpu_to->of_clk.rate = timer_of_rate(to);
+ cpu_to->clkevt.cpumask = cpumask_of(cpu);
+ cpu_to->clkevt.irq =
+ irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+ if (!cpu_to->clkevt.irq) {
+ pr_err("%s: can't map IRQ for CPU%d\n",
+ __func__, cpu);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
+ ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
+ IRQF_TIMER | IRQF_NOBALANCING,
+ cpu_to->clkevt.name, &cpu_to->clkevt);
+ if (ret) {
+ pr_err("%s: cannot setup irq %d for CPU%d\n",
+ __func__, cpu_to->clkevt.irq, cpu);
+ ret = -EINVAL;
+ goto out_irq;
+ }
+ }
+
+ cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+ "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+ tegra_timer_stop);
+
+ return ret;
+out_irq:
+ for_each_possible_cpu(cpu) {
+ struct timer_of *cpu_to;
+
+ cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ if (cpu_to->clkevt.irq) {
+ free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
+ irq_dispose_mapping(cpu_to->clkevt.irq);
+ }
}
+out:
+ timer_of_cleanup(to);
+ return ret;
+}
+#else /* CONFIG_ARM */
+static int __init tegra_init_timer(struct device_node *np)
+{
+ int ret = 0;
+
+ ret = tegra_timer_common_init(np, &tegra_to);
+ if (ret < 0)
+ goto out;

- sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+ tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
+ tegra_to.of_clk.rate = 1000000; /* microsecond timer */

+ sched_clock_register(tegra_read_sched_clock, 32,
+ timer_of_rate(&tegra_to));
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
- "timer_us", 1000000, 300, 32,
- clocksource_mmio_readl_up);
+ "timer_us", timer_of_rate(&tegra_to),
+ 300, 32, clocksource_mmio_readl_up);
if (ret) {
pr_err("Failed to register clocksource\n");
- return ret;
+ goto out;
}

tegra_delay_timer.read_current_timer =
tegra_delay_timer_read_counter_long;
- tegra_delay_timer.freq = 1000000;
+ tegra_delay_timer.freq = timer_of_rate(&tegra_to);
register_current_timer_delay(&tegra_delay_timer);

- ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
- if (ret) {
- pr_err("Failed to register timer IRQ: %d\n", ret);
- return ret;
- }
+ clockevents_config_and_register(&tegra_to.clkevt,
+ timer_of_rate(&tegra_to),
+ 0x1,
+ 0x1fffffff);

- tegra_clockevent.cpumask = cpu_possible_mask;
- tegra_clockevent.irq = tegra_timer_irq.irq;
- clockevents_config_and_register(&tegra_clockevent, 1000000,
- 0x1, 0x1fffffff);
+ return ret;
+out:
+ timer_of_cleanup(&tegra_to);

- return 0;
+ return ret;
}
-TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);

static int __init tegra20_init_rtc(struct device_node *np)
{
@@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np)
return register_persistent_clock(tegra_read_persistent_clock64);
}
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+#endif
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
+TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index fe4481676da6..a0b03443d8c1 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC
select PINCTRL_TEGRA210
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
+ select TEGRA_TIMER
help
Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index fd586d0301e7..e78281d07b70 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -121,6 +121,7 @@ enum cpuhp_state {
CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
CPUHP_AP_ARM_TWD_STARTING,
CPUHP_AP_QCOM_TIMER_STARTING,
+ CPUHP_AP_TEGRA_TIMER_STARTING,
CPUHP_AP_ARMADA_TIMER_STARTING,
CPUHP_AP_MARCO_TIMER_STARTING,
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h
index e96581ca7c9d..b20798fc5191 100644
--- a/include/linux/posix-timers.h
+++ b/include/linux/posix-timers.h
@@ -12,7 +12,7 @@ struct siginfo;

struct cpu_timer_list {
struct list_head entry;
- u64 expires, incr;
+ u64 expires;
struct task_struct *task;
int firing;
};
diff --git a/kernel/rcu/Kconfig b/kernel/rcu/Kconfig
index 939a2056c87a..37301430970e 100644
--- a/kernel/rcu/Kconfig
+++ b/kernel/rcu/Kconfig
@@ -87,36 +87,6 @@ config RCU_STALL_COMMON
config RCU_NEED_SEGCBLIST
def_bool ( TREE_RCU || PREEMPT_RCU || TREE_SRCU )

-config CONTEXT_TRACKING
- bool
-
-config CONTEXT_TRACKING_FORCE
- bool "Force context tracking"
- depends on CONTEXT_TRACKING
- default y if !NO_HZ_FULL
- help
- The major pre-requirement for full dynticks to work is to
- support the context tracking subsystem. But there are also
- other dependencies to provide in order to make the full
- dynticks working.
-
- This option stands for testing when an arch implements the
- context tracking backend but doesn't yet fullfill all the
- requirements to make the full dynticks feature working.
- Without the full dynticks, there is no way to test the support
- for context tracking and the subsystems that rely on it: RCU
- userspace extended quiescent state and tickless cputime
- accounting. This option copes with the absence of the full
- dynticks subsystem by forcing the context tracking on all
- CPUs in the system.
-
- Say Y only if you're working on the development of an
- architecture backend for the context tracking.
-
- Say N otherwise, this option brings an overhead that you
- don't want in production.
-
-
config RCU_FANOUT
int "Tree-based hierarchical RCU fanout value"
range 2 64 if 64BIT
diff --git a/kernel/time/Kconfig b/kernel/time/Kconfig
index 58b981f4bb5d..e2c038d6c13c 100644
--- a/kernel/time/Kconfig
+++ b/kernel/time/Kconfig
@@ -117,6 +117,35 @@ config NO_HZ_FULL

endchoice

+config CONTEXT_TRACKING
+ bool
+
+config CONTEXT_TRACKING_FORCE
+ bool "Force context tracking"
+ depends on CONTEXT_TRACKING
+ default y if !NO_HZ_FULL
+ help
+ The major pre-requirement for full dynticks to work is to
+ support the context tracking subsystem. But there are also
+ other dependencies to provide in order to make the full
+ dynticks working.
+
+ This option stands for testing when an arch implements the
+ context tracking backend but doesn't yet fullfill all the
+ requirements to make the full dynticks feature working.
+ Without the full dynticks, there is no way to test the support
+ for context tracking and the subsystems that rely on it: RCU
+ userspace extended quiescent state and tickless cputime
+ accounting. This option copes with the absence of the full
+ dynticks subsystem by forcing the context tracking on all
+ CPUs in the system.
+
+ Say Y only if you're working on the development of an
+ architecture backend for the context tracking.
+
+ Say N otherwise, this option brings an overhead that you
+ don't want in production.
+
config NO_HZ
bool "Old Idle dynticks config"
depends on !ARCH_USES_GETTIMEOFFSET && GENERIC_CLOCKEVENTS
diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c
index f5cfa1b73d6f..6418e1bdc549 100644
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -364,7 +364,7 @@ static bool hrtimer_fixup_activate(void *addr, enum debug_obj_state state)
switch (state) {
case ODEBUG_STATE_ACTIVE:
WARN_ON(1);
-
+ /* fall through */
default:
return false;
}
diff --git a/kernel/time/posix-cpu-timers.c b/kernel/time/posix-cpu-timers.c
index 80f955210861..0a426f4e3125 100644
--- a/kernel/time/posix-cpu-timers.c
+++ b/kernel/time/posix-cpu-timers.c
@@ -67,13 +67,13 @@ static void bump_cpu_timer(struct k_itimer *timer, u64 now)
int i;
u64 delta, incr;

- if (timer->it.cpu.incr == 0)
+ if (!timer->it_interval)
return;

if (now < timer->it.cpu.expires)
return;

- incr = timer->it.cpu.incr;
+ incr = timer->it_interval;
delta = now + incr - timer->it.cpu.expires;

/* Don't use (incr*2 < delta), incr*2 might overflow. */
@@ -520,7 +520,7 @@ static void cpu_timer_fire(struct k_itimer *timer)
*/
wake_up_process(timer->it_process);
timer->it.cpu.expires = 0;
- } else if (timer->it.cpu.incr == 0) {
+ } else if (!timer->it_interval) {
/*
* One-shot timer. Clear it as soon as it's fired.
*/
@@ -606,7 +606,7 @@ static int posix_cpu_timer_set(struct k_itimer *timer, int timer_flags,
*/

ret = 0;
- old_incr = timer->it.cpu.incr;
+ old_incr = timer->it_interval;
old_expires = timer->it.cpu.expires;
if (unlikely(timer->it.cpu.firing)) {
timer->it.cpu.firing = -1;
@@ -684,8 +684,7 @@ static int posix_cpu_timer_set(struct k_itimer *timer, int timer_flags,
* Install the new reload setting, and
* set up the signal and overrun bookkeeping.
*/
- timer->it.cpu.incr = timespec64_to_ns(&new->it_interval);
- timer->it_interval = ns_to_ktime(timer->it.cpu.incr);
+ timer->it_interval = timespec64_to_ktime(new->it_interval);

/*
* This acts as a modification timestamp for the timer,
@@ -724,7 +723,7 @@ static void posix_cpu_timer_get(struct k_itimer *timer, struct itimerspec64 *itp
/*
* Easy part: convert the reload time.
*/
- itp->it_interval = ns_to_timespec64(timer->it.cpu.incr);
+ itp->it_interval = ktime_to_timespec64(timer->it_interval);

if (!timer->it.cpu.expires)
return;
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index 803fa67aace9..ee834d4fb814 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -375,6 +375,7 @@ void tick_broadcast_control(enum tick_broadcast_mode mode)
switch (mode) {
case TICK_BROADCAST_FORCE:
tick_broadcast_forced = 1;
+ /* fall through */
case TICK_BROADCAST_ON:
cpumask_set_cpu(cpu, tick_broadcast_on);
if (!cpumask_test_and_set_cpu(cpu, tick_broadcast_mask)) {
diff --git a/kernel/time/timekeeping_debug.c b/kernel/time/timekeeping_debug.c
index 86489950d690..b73e8850e58d 100644
--- a/kernel/time/timekeeping_debug.c
+++ b/kernel/time/timekeeping_debug.c
@@ -37,15 +37,8 @@ DEFINE_SHOW_ATTRIBUTE(tk_debug_sleep_time);

static int __init tk_debug_sleep_time_init(void)
{
- struct dentry *d;
-
- d = debugfs_create_file("sleep_time", 0444, NULL, NULL,
- &tk_debug_sleep_time_fops);
- if (!d) {
- pr_err("Failed to create sleep_time debug file\n");
- return -ENOMEM;
- }
-
+ debugfs_create_file("sleep_time", 0444, NULL, NULL,
+ &tk_debug_sleep_time_fops);
return 0;
}
late_initcall(tk_debug_sleep_time_init);
diff --git a/kernel/time/timer.c b/kernel/time/timer.c
index 444156debfa0..167e71f9ed3c 100644
--- a/kernel/time/timer.c
+++ b/kernel/time/timer.c
@@ -647,7 +647,7 @@ static bool timer_fixup_activate(void *addr, enum debug_obj_state state)

case ODEBUG_STATE_ACTIVE:
WARN_ON(1);
-
+ /* fall through */
default:
return false;
}

--
Greetings ,

How you doing? Hope you are alright, I sent you message earlier but no
response from you, did you receive my First email to you? I am
expecting your reply as soon as you receive this email massage
(douggross55@gmail.com ),

Best Regards,

Doug Gross

--
Did you receive my previous message ?
Please reply to me.
______________________

?? ????? ?????? ????????
?????? ???? ???

Because of this change, the driver now expects a pinctrl device
reference in the mmc controller's device tree node; without it, it will
bail out. This could break existing setups that don't specify it
because it "just worked" up until now. So currently I just let the old
behavior fall away because this is a staging driver. But if this is a
problem, the old behavior could be added back as a fallback.

This is version 2 of a patchset that I requested feedback for about a
month ago. Please review as if they are a new patchset; all the patches
were rebased several times and a couple new correctness fixes added.

The TODO list is largely unchanged, aside from the couple of TODO
comments in the code that I have addressed. Ultimately, I think this
driver could potentially be merged with the "real" mtk-mmc driver as the
TODO suggests, but someone who is more familiar with the IP core will
have to do that. Mediatek documentation (that I can find) is very
sparse.

This is ready to merge if there is no other feedback!

From George Hilliard <thirtythreeforty@gmail.com> # This line is ignored.
From: George Hilliard <thirtythreeforty@gmail.com>
Reply-To:
Subject: [PATCH v2 00/11] mt7621-mmc: Various correctness fixes
In-Reply-To:

Date: Tue, 19 Mar 2019 14:45:45 +0200
Subject: [PATCH 0/9] RFC: NVME VFIO mediated device

Hi everyone!

In this patch series, I would like to introduce my take on the problem of doing
as fast as possible virtualization of storage with emphasis on low latency.

In this patch series I implemented a kernel vfio based, mediated device that
allows the user to pass through a partition and/or whole namespace to a guest.

The idea behind this driver is based on paper you can find at
https://www.usenix.org/conference/atc18/presentation/peng,

Although note that I stared the development prior to reading this paper,
independently.

In addition to that implementation is not based on code used in the paper as
I wasn't being able at that time to make the source available to me.

***Key points about the implementation:***

* Polling kernel thread is used. The polling is stopped after a
predefined timeout (1/2 sec by default).
Support for all interrupt driven mode is planned, and it shows promising results.

* Guest sees a standard NVME device - this allows to run guest with
unmodified drivers, for example windows guests.

* The NVMe device is shared between host and guest.
That means that even a single namespace can be split between host
and guest based on different partitions.

* Simple configuration

*** Performance ***

Performance was tested on Intel DC P3700, With Xeon E5-2620 v2
and both latency and throughput is very similar to SPDK.

Soon I will test this on a better server and nvme device and provide
more formal performance numbers.

Latency numbers:
~80ms - spdk with fio plugin on the host.
~84ms - nvme driver on the host
~87ms - mdev-nvme + nvme driver in the guest

Throughput was following similar pattern as well.

* Configuration example
$ modprobe nvme mdev_queues=4
$ modprobe nvme-mdev

$ UUID=$(uuidgen)
$ DEVICE='device pci address'
$ echo $UUID > /sys/bus/pci/devices/$DEVICE/mdev_supported_types/nvme-2Q_V1/create
$ echo n1p3 > /sys/bus/mdev/devices/$UUID/namespaces/add_namespace #attach host namespace 1 parition 3
$ echo 11 > /sys/bus/mdev/devices/$UUID/settings/iothread_cpu #pin the io thread to cpu 11

Afterward boot qemu with
-device vfio-pci,sysfsdev=/sys/bus/mdev/devices/$UUID

Zero configuration on the guest.

*** FAQ ***

* Why to make this in the kernel? Why this is better that SPDK

-> Reuse the existing nvme kernel driver in the host. No new drivers in the guest.

-> Share the NVMe device between host and guest.
Even in fully virtualized configurations,
some partitions of nvme device could be used by guests as block devices
while others passed through with nvme-mdev to achieve balance between
all features of full IO stack emulation and performance.

-> NVME-MDEV is a bit faster due to the fact that in-kernel driver
can send interrupts to the guest directly without a context
switch that can be expensive due to meltdown mitigation.

-> Is able to utilize interrupts to get reasonable performance.
This is only implemented
as a proof of concept and not included in the patches,
but interrupt driven mode shows reasonable performance

-> This is a framework that later can be used to support NVMe devices
with more of the IO virtualization built-in
(IOMMU with PASID support coupled with device that supports it)

* Why to attach directly to nvme-pci driver and not use block layer IO
-> The direct attachment allows for better performance, but I will
check the possibility of using block IO, especially for fabrics drivers.

*** Implementation notes ***

* All guest memory is mapped into the physical nvme device
but not 1:1 as vfio-pci would do this.
This allows very efficient DMA.
To support this, patch 2 adds ability for a mdev device to listen on
guest's memory map events.
Any such memory is immediately pinned and then DMA mapped.
(Support for fabric drivers where this is not possible exits too,
in which case the fabric driver will do its own DMA mapping)

* nvme core driver is modified to announce the appearance
and disappearance of nvme controllers and namespaces,
to which the nvme-mdev driver is subscribed.

* nvme-pci driver is modified to expose raw interface of attaching to
and sending/polling the IO queues.
This allows the mdev driver very efficiently to submit/poll for the IO.
By default one host queue is used per each mediated device.
(support for other fabric based host drivers is planned)

* The nvme-mdev doesn't assume presence of KVM, thus any VFIO user, including
SPDK, a qemu running with tccg, ... can use this virtual device.

*** Testing ***

The device was tested with stock QEMU 3.0 on the host,
with host was using 5.0 kernel with nvme-mdev added and the following hardware:
* QEMU nvme virtual device (with nested guest)
* Intel DC P3700 on Xeon E5-2620 v2 server
* Samsung SM981 (in a Thunderbolt enclosure, with my laptop)
* Lenovo NVME device found in my laptop

The guest was tested with kernel 4.16, 4.18, 4.20 and
the same custom complied kernel 5.0
Windows 10 guest was tested too with both Microsoft's inbox driver and
open source community NVME driver
(https://lists.openfabrics.org/pipermail/nvmewin/2016-December/001420.html)

Testing was mostly done on x86_64, but 32 bit host/guest combination
was lightly tested too.

In addition to that, the virtual device was tested with nested guest,
by passing the virtual device to it,
using pci passthrough, qemu userspace nvme driver, and spdk


PS: I used to contribute to the kernel as a hobby using the
maximlevitsky@gmail.com address

Maxim Levitsky (9):
vfio/mdev: add .request callback
nvme/core: add some more values from the spec
nvme/core: add NVME_CTRL_SUSPENDED controller state
nvme/pci: use the NVME_CTRL_SUSPENDED state
nvme/pci: add known admin effects to augument admin effects log page
nvme/pci: init shadow doorbell after each reset
nvme/core: add mdev interfaces
nvme/core: add nvme-mdev core driver
nvme/pci: implement the mdev external queue allocation interface

MAINTAINERS | 5 +
drivers/nvme/Kconfig | 1 +
drivers/nvme/Makefile | 1 +
drivers/nvme/host/core.c | 149 +++++-
drivers/nvme/host/nvme.h | 55 ++-
drivers/nvme/host/pci.c | 385 ++++++++++++++-
drivers/nvme/mdev/Kconfig | 16 +
drivers/nvme/mdev/Makefile | 5 +
drivers/nvme/mdev/adm.c | 873 ++++++++++++++++++++++++++++++++++
drivers/nvme/mdev/events.c | 142 ++++++
drivers/nvme/mdev/host.c | 491 +++++++++++++++++++
drivers/nvme/mdev/instance.c | 802 +++++++++++++++++++++++++++++++
drivers/nvme/mdev/io.c | 563 ++++++++++++++++++++++
drivers/nvme/mdev/irq.c | 264 ++++++++++
drivers/nvme/mdev/mdev.h | 56 +++
drivers/nvme/mdev/mmio.c | 591 +++++++++++++++++++++++
drivers/nvme/mdev/pci.c | 247 ++++++++++
drivers/nvme/mdev/priv.h | 700 +++++++++++++++++++++++++++
drivers/nvme/mdev/udata.c | 390 +++++++++++++++
drivers/nvme/mdev/vcq.c | 207 ++++++++
drivers/nvme/mdev/vctrl.c | 514 ++++++++++++++++++++
drivers/nvme/mdev/viommu.c | 322 +++++++++++++
drivers/nvme/mdev/vns.c | 356 ++++++++++++++
drivers/nvme/mdev/vsq.c | 178 +++++++
drivers/vfio/mdev/vfio_mdev.c | 11 +
include/linux/mdev.h | 4 +
include/linux/nvme.h | 88 +++-
27 files changed, 7375 insertions(+), 41 deletions(-)
create mode 100644 drivers/nvme/mdev/Kconfig
create mode 100644 drivers/nvme/mdev/Makefile
create mode 100644 drivers/nvme/mdev/adm.c
create mode 100644 drivers/nvme/mdev/events.c
create mode 100644 drivers/nvme/mdev/host.c
create mode 100644 drivers/nvme/mdev/instance.c
create mode 100644 drivers/nvme/mdev/io.c
create mode 100644 drivers/nvme/mdev/irq.c
create mode 100644 drivers/nvme/mdev/mdev.h
create mode 100644 drivers/nvme/mdev/mmio.c
create mode 100644 drivers/nvme/mdev/pci.c
create mode 100644 drivers/nvme/mdev/priv.h
create mode 100644 drivers/nvme/mdev/udata.c
create mode 100644 drivers/nvme/mdev/vcq.c
create mode 100644 drivers/nvme/mdev/vctrl.c
create mode 100644 drivers/nvme/mdev/viommu.c
create mode 100644 drivers/nvme/mdev/vns.c
create mode 100644 drivers/nvme/mdev/vsq.c

--
2.17.2

On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> -> Share the NVMe device between host and guest.
> Even in fully virtualized configurations,
> some partitions of nvme device could be used by guests as block devices
> while others passed through with nvme-mdev to achieve balance between
> all features of full IO stack emulation and performance.
>
> -> NVME-MDEV is a bit faster due to the fact that in-kernel driver
> can send interrupts to the guest directly without a context
> switch that can be expensive due to meltdown mitigation.
>
> -> Is able to utilize interrupts to get reasonable performance.
> This is only implemented
> as a proof of concept and not included in the patches,
> but interrupt driven mode shows reasonable performance
>
> -> This is a framework that later can be used to support NVMe devices
> with more of the IO virtualization built-in
> (IOMMU with PASID support coupled with device that supports it)

Would be very interested to see the PASID support. You wouldn't even
need to mediate the IO doorbells or translations if assigning entire
namespaces, and should be much faster than the shadow doorbells.

I think you should send 6/9 "nvme/pci: init shadow doorbell after each
reset" separately for immediate inclusion.

I like the idea in principle, but it will take me a little time to get
through reviewing your implementation. I would have guessed we could
have leveraged something from the existing nvme/target for the mediating
controller register access and admin commands. Maybe even start with
implementing an nvme passthrough namespace target type (we currently
have block and file).

Hi Keith,
On 03/19/2019 08:21 AM, Keith Busch wrote:
> On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
>> -> Share the NVMe device between host and guest.
>> Even in fully virtualized configurations,
>> some partitions of nvme device could be used by guests as block devices
>> while others passed through with nvme-mdev to achieve balance between
>> all features of full IO stack emulation and performance.
>>
>> -> NVME-MDEV is a bit faster due to the fact that in-kernel driver
>> can send interrupts to the guest directly without a context
>> switch that can be expensive due to meltdown mitigation.
>>
>> -> Is able to utilize interrupts to get reasonable performance.
>> This is only implemented
>> as a proof of concept and not included in the patches,
>> but interrupt driven mode shows reasonable performance
>>
>> -> This is a framework that later can be used to support NVMe devices
>> with more of the IO virtualization built-in
>> (IOMMU with PASID support coupled with device that supports it)
>
> Would be very interested to see the PASID support. You wouldn't even
> need to mediate the IO doorbells or translations if assigning entire
> namespaces, and should be much faster than the shadow doorbells.
>
> I think you should send 6/9 "nvme/pci: init shadow doorbell after each
> reset" separately for immediate inclusion.
>
> I like the idea in principle, but it will take me a little time to get
> through reviewing your implementation. I would have guessed we could
> have leveraged something from the existing nvme/target for the mediating
> controller register access and admin commands. Maybe even start with
> implementing an nvme passthrough namespace target type (we currently
> have block and file).

I have the code for the NVMeOf target passthru-ctrl, I think we can use
that as it is if you are looking for the passthru for NVMeOF.

I'll post patch-series based on the latest code base soon.
>
> _______________________________________________
> Linux-nvme mailing list
> Linux-nvme@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-nvme
>

On Mon, Mar 18, 2019 at 08:20:01PM -0600, George Hilliard wrote:
> Because of this change, the driver now expects a pinctrl device
> reference in the mmc controller's device tree node; without it, it will
> bail out. This could break existing setups that don't specify it
> because it "just worked" up until now. So currently I just let the old
> behavior fall away because this is a staging driver. But if this is a
> problem, the old behavior could be added back as a fallback.
>
> This is version 2 of a patchset that I requested feedback for about a
> month ago. Please review as if they are a new patchset; all the patches
> were rebased several times and a couple new correctness fixes added.
>
> The TODO list is largely unchanged, aside from the couple of TODO
> comments in the code that I have addressed. Ultimately, I think this
> driver could potentially be merged with the "real" mtk-mmc driver as the
> TODO suggests, but someone who is more familiar with the IP core will
> have to do that. Mediatek documentation (that I can find) is very
> sparse.
>
> This is ready to merge if there is no other feedback!
>
> >From George Hilliard <thirtythreeforty@gmail.com> # This line is ignored.
> From: George Hilliard <thirtythreeforty@gmail.com>
> Reply-To:
> Subject: [PATCH v2 00/11] mt7621-mmc: Various correctness fixes
> In-Reply-To:
>
>

No subject for this email?

On Tue, 2019-03-19 at 16:41 +-0200, Maxim Levitsky wrote:
+AD4 +ACo Polling kernel thread is used. The polling is stopped after a
+AD4 predefined timeout (1/2 sec by default).
+AD4 Support for all interrupt driven mode is planned, and it shows promising results.

Which cgroup will the CPU cycles used for polling be attributed to? Can the
polling code be moved into user space such that it becomes easy to identify
which process needs most CPU cycles for polling and such that the polling
CPU cycles are attributed to the proper cgroup?

Thanks,

Bart.

On Tue, 2019-03-19 at 16:41 +-0200, Maxim Levitsky wrote:
+AD4 +ACo All guest memory is mapped into the physical nvme device
+AD4 but not 1:1 as vfio-pci would do this.
+AD4 This allows very efficient DMA.
+AD4 To support this, patch 2 adds ability for a mdev device to listen on
+AD4 guest's memory map events.
+AD4 Any such memory is immediately pinned and then DMA mapped.
+AD4 (Support for fabric drivers where this is not possible exits too,
+AD4 in which case the fabric driver will do its own DMA mapping)

Does this mean that all guest memory is pinned all the time? If so, are you
sure that's acceptable?

Additionally, what is the performance overhead of the IOMMU notifier added
by patch 8/9? How often was that notifier called per second in your tests
and how much time was spent per call in the notifier callbacks?

Thanks,

Bart.

On Tue, 2019-03-19 at 09:22 -0600, Keith Busch wrote:
> On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> > -> Share the NVMe device between host and guest.
> > Even in fully virtualized configurations,
> > some partitions of nvme device could be used by guests as block
> > devices
> > while others passed through with nvme-mdev to achieve balance between
> > all features of full IO stack emulation and performance.
> >
> > -> NVME-MDEV is a bit faster due to the fact that in-kernel driver
> > can send interrupts to the guest directly without a context
> > switch that can be expensive due to meltdown mitigation.
> >
> > -> Is able to utilize interrupts to get reasonable performance.
> > This is only implemented
> > as a proof of concept and not included in the patches,
> > but interrupt driven mode shows reasonable performance
> >
> > -> This is a framework that later can be used to support NVMe devices
> > with more of the IO virtualization built-in
> > (IOMMU with PASID support coupled with device that supports it)
>

> Would be very interested to see the PASID support. You wouldn't even
> need to mediate the IO doorbells or translations if assigning entire
> namespaces, and should be much faster than the shadow doorbells.

I fully agree with that.
Note that to enable PASID support two things have to happen in this vendor.

1. Mature support for IOMMU with PASID support. On Intel side I know that they
only have a spec released and currently the kernel bits to support it are
placed.
I still don't know when a product actually supporting this spec is going to be
released. For other vendors (ARM/AMD/) I haven't done yet a research on state of
PASID based IOMMU support on their platforms.

2. NVMe spec has to be extended to support PASID. At minimum, we need an ability
to assign an PASID to a sq/cq queue pair and ability to relocate the doorbells,
such as each guest would get its own (hardware backed) MMIO page with its own
doorbells. Plus of course the hardware vendors have to embrace the spec. I guess
these two things will happen in collaborative manner.


>
> I think you should send 6/9 "nvme/pci: init shadow doorbell after each
> reset" separately for immediate inclusion.
I'll do this soon.

Also '5/9 nvme/pci: add known admin effects to augment admin effects log page'
can be considered for immediate inclusion as well, as it works around a flaw
in the NVMe controller badly done admin side effects page with no side effects
(pun intended) for spec compliant controllers (I think so).

This can be fixed with a quirk if you prefer though.

>
> I like the idea in principle, but it will take me a little time to get
> through reviewing your implementation. I would have guessed we could
> have leveraged something from the existing nvme/target for the mediating
> controller register access and admin commands. Maybe even start with
> implementing an nvme passthrough namespace target type (we currently
> have block and file).

I fully agree with you on that I could have used some of the nvme/target code,
and I am planning to do so eventually.

For that I would need to make my driver, to be one of the target drivers, and I
would need to add another target back end, like you said to allow my target
driver to talk directly to the nvme hardware bypassing the block layer.

Or instead I can use the block backend,
(but note that currently the block back-end doesn't support polling which is
critical for the performance).

Switch to the target code might though have some (probably minor) performance
impact, as it would probably lengthen the critical code path a bit (I might need
for instance to translate the PRP lists I am getting from the virtual controller
to a scattergather list and back).

This is why I did this the way I did, but now knowing that probably I can afford
to loose a bit of performance, I can look at doing that.

Best regards,
Thanks in advance for the review,
Maxim Levitsky

PS:

For reference currently the IO path looks more or less like that:

My IO thread notices a doorbell write, reads a command from a submission queue,
translates it (without even looking at the data pointer) and sends it to the
nvme pci driver together with pointer to data iterator'.

The nvme pci driver calls the data iterator N times, which makes the iterator
translate and fetch the DMA addresses where the data is already mapped on the
its pci nvme device (the mdev driver maps all the guest memory to the nvme pci
device).
The nvme pci driver uses these addresses it receives, to create a prp list,
which it puts into the data pointer.

The nvme pci driver also allocates an free command id, from a list, puts it into
the command ID and sends the command to the real hardware.

Later the IO thread calls to the nvme pci driver to poll the queue. When
completions arrive, the nvme pci driver returns them back to the IO thread.

>
> _______________________________________________
> Linux-nvme mailing list
> Linux-nvme@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-nvme

On Wed, 2019-03-20 at 08:28 -0700, Bart Van Assche wrote:
> On Tue, 2019-03-19 at 16:41 +0200, Maxim Levitsky wrote:
> > * All guest memory is mapped into the physical nvme device
> > but not 1:1 as vfio-pci would do this.
> > This allows very efficient DMA.
> > To support this, patch 2 adds ability for a mdev device to listen on
> > guest's memory map events.
> > Any such memory is immediately pinned and then DMA mapped.
> > (Support for fabric drivers where this is not possible exits too,
> > in which case the fabric driver will do its own DMA mapping)
>
> Does this mean that all guest memory is pinned all the time? If so, are you
> sure that's acceptable?
I think so. The VFIO pci passthrough also pins all the guest memory.
SPDK also does this (pins and dma maps) all the guest memory.

I agree that this is not an ideal solution but this is a fastest and simplest
solution possible.

>
> Additionally, what is the performance overhead of the IOMMU notifier added
> by patch 8/9? How often was that notifier called per second in your tests
> and how much time was spent per call in the notifier callbacks?

To be honest I haven't optimized my IOMMU notifier at all, so when it is called,
it stops the IO thread, does its work and then restarts it which is very slow.

Fortunelly it is not called at all during normal operation as VFIO dma map/unmap
events are really rare and happen only on guest boot.

The same is even true for nested guests, as nested guest startup causes a wave
of map unmap events while shadow IOMMU updates, but then it just uses these
mapping without changing them.

The only case when performance is really bad is when you boot a guest with
iommu=on intel_iommu=on and then use the nvme driver there. In this case, the
driver in the guest does itself IOMMU maps/unmaps (on the virtual IOMMU) and for
each such event my VFIO map/unmap callback is called.

This can be optimized though to be much better using also some kind of queued
invalidation in my driver. iommu=pt meanwhile in the guest solves that issue.

Best regards,
Maxim Levitsky

>
> Thanks,
>
> Bart.
>
> _______________________________________________
> Linux-nvme mailing list
> Linux-nvme@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-nvme

On Tue, 2019-03-19 at 23:49 +0000, Chaitanya Kulkarni wrote:
> Hi Keith,
> On 03/19/2019 08:21 AM, Keith Busch wrote:
> > On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> > > -> Share the NVMe device between host and guest.
> > > Even in fully virtualized configurations,
> > > some partitions of nvme device could be used by guests as block
> > > devices
> > > while others passed through with nvme-mdev to achieve balance
> > > between
> > > all features of full IO stack emulation and performance.
> > >
> > > -> NVME-MDEV is a bit faster due to the fact that in-kernel driver
> > > can send interrupts to the guest directly without a context
> > > switch that can be expensive due to meltdown mitigation.
> > >
> > > -> Is able to utilize interrupts to get reasonable performance.
> > > This is only implemented
> > > as a proof of concept and not included in the patches,
> > > but interrupt driven mode shows reasonable performance
> > >
> > > -> This is a framework that later can be used to support NVMe devices
> > > with more of the IO virtualization built-in
> > > (IOMMU with PASID support coupled with device that supports it)
> >
> > Would be very interested to see the PASID support. You wouldn't even
> > need to mediate the IO doorbells or translations if assigning entire
> > namespaces, and should be much faster than the shadow doorbells.
> >
> > I think you should send 6/9 "nvme/pci: init shadow doorbell after each
> > reset" separately for immediate inclusion.
> >
> > I like the idea in principle, but it will take me a little time to get
> > through reviewing your implementation. I would have guessed we could
> > have leveraged something from the existing nvme/target for the mediating
> > controller register access and admin commands. Maybe even start with
> > implementing an nvme passthrough namespace target type (we currently
> > have block and file).
>
> I have the code for the NVMeOf target passthru-ctrl, I think we can use
> that as it is if you are looking for the passthru for NVMeOF.
>
> I'll post patch-series based on the latest code base soon.

I am very intersing in this code.
Could you explain how your NVMeOF target passthrough works?
Which components of the NVME stack does it involve?

Best regards,
Maxim Levitsky

> >
> > _______________________________________________
> > Linux-nvme mailing list
> > Linux-nvme@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-nvme
> >
>
>
> _______________________________________________
> Linux-nvme mailing list
> Linux-nvme@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-nvme

On Wed, 2019-03-20 at 08:08 -0700, Bart Van Assche wrote:
> On Tue, 2019-03-19 at 16:41 +0200, Maxim Levitsky wrote:
> > * Polling kernel thread is used. The polling is stopped after a
> > predefined timeout (1/2 sec by default).
> > Support for all interrupt driven mode is planned, and it shows promising
> > results.
>
> Which cgroup will the CPU cycles used for polling be attributed to? Can the
> polling code be moved into user space such that it becomes easy to identify
> which process needs most CPU cycles for polling and such that the polling
> CPU cycles are attributed to the proper cgroup?


Currently there is a single IO thread per each virtual controller instance.
I would prefer to keep all the driver in the kernel, but I think I can make it
cgroup aware, in a simiar way this is done in vhost-net, and vhost-scsi.

Best regards,
Maxim Levitsky


> Thanks,
>
> Bart.

On Wed, Mar 20, 2019 at 06:30:29PM +0200, Maxim Levitsky wrote:
> Or instead I can use the block backend,
> (but note that currently the block back-end doesn't support polling which is
> critical for the performance).

Oh, I think you can do polling through there. For reference, fs/io_uring.c
has a pretty good implementation that aligns with how you could use it.

On Wed, 2019-03-20 at 11:03 -0600, Keith Busch wrote:
> On Wed, Mar 20, 2019 at 06:30:29PM +0200, Maxim Levitsky wrote:
> > Or instead I can use the block backend,
> > (but note that currently the block back-end doesn't support polling which is
> > critical for the performance).
>
> Oh, I think you can do polling through there. For reference, fs/io_uring.c
> has a pretty good implementation that aligns with how you could use it.


That is exactly my thought. The polling recently got lot of improvements in the
block layer, which migh make this feasable.

I will give it a try.

Best regards,
Maxim Levitsky

subscribe linux-kernel

Date: Thu, 21 Mar 2019 10:14:34 +0800
Subject: [PATCH] MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices

For a long time the mt7621 uses a fixed cpu clock which causes a problem
if the cpu frequency is not 880MHz.

This patch fixes the cpu clock calculation and adds the cpu/bus clkdev
which will be used in dts.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>

Ported from OpenWrt:
c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++
arch/mips/ralink/mt7621.c | 102 ++++++++++++++-------
arch/mips/ralink/timer-gic.c | 4 +-
3 files changed, 93 insertions(+), 33 deletions(-)

diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
index a672e06fa5fd..b8a8834164c8 100644
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -19,6 +19,10 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0 0x2c
+#define SYSC_REG_CUR_CLK_STS 0x44
+
+#define MEMC_REG_CPU_PLL 0x648

#define CHIP_REV_PKG_MASK 0x1
#define CHIP_REV_PKG_SHIFT 16
@@ -26,6 +30,22 @@
#define CHIP_REV_VER_SHIFT 8
#define CHIP_REV_ECO_MASK 0xf

+#define XTAL_MODE_SEL_MASK 0x7
+#define XTAL_MODE_SEL_SHIFT 6
+
+#define CPU_CLK_SEL_MASK 0x3
+#define CPU_CLK_SEL_SHIFT 30
+
+#define CUR_CPU_FDIV_MASK 0x1f
+#define CUR_CPU_FDIV_SHIFT 8
+#define CUR_CPU_FFRAC_MASK 0x1f
+#define CUR_CPU_FFRAC_SHIFT 0
+
+#define CPU_PLL_PREDIV_MASK 0x3
+#define CPU_PLL_PREDIV_SHIFT 12
+#define CPU_PLL_FBDIV_MASK 0x7f
+#define CPU_PLL_FBDIV_SHIFT 4
+
#define MT7621_DRAM_BASE 0x0
#define MT7621_DDR2_SIZE_MIN 32
#define MT7621_DDR2_SIZE_MAX 256
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index d2718de60b9b..0b2845a4a036 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -9,22 +9,22 @@

#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <dt-bindings/clock/mt7621-clk.h>

#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
#include <asm/mips-cps.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
+#include <asm/time.h>

#include <pinmux.h>

#include "common.h"

-#define SYSC_REG_SYSCFG 0x10
-#define SYSC_REG_CPLL_CLKCFG0 0x2c
-#define SYSC_REG_CUR_CLK_STS 0x44
-#define CPU_CLK_SEL (BIT(30) | BIT(31))
-
#define MT7621_GPIO_MODE_UART1 1
#define MT7621_GPIO_MODE_I2C 2
#define MT7621_GPIO_MODE_UART3_MASK 0x3
@@ -110,49 +110,90 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = {
{ 0 }
};

+static struct clk *clks[MT7621_CLK_MAX];
+static struct clk_onecell_data clk_data = {
+ .clks = clks,
+ .clk_num = ARRAY_SIZE(clks),
+};
+
phys_addr_t mips_cpc_default_phys_base(void)
{
panic("Cannot detect cpc address");
}

+static struct clk *__init mt7621_add_sys_clkdev(
+ const char *id, unsigned long rate)
+{
+ struct clk *clk;
+ int err;
+
+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
+ if (IS_ERR(clk))
+ panic("failed to allocate %s clock structure", id);
+
+ err = clk_register_clkdev(clk, id, NULL);
+ if (err)
+ panic("unable to register %s clock device", id);
+
+ return clk;
+}
+
void __init ralink_clk_init(void)
{
- int cpu_fdiv = 0;
- int cpu_ffrac = 0;
- int fbdiv = 0;
- u32 clk_sts, syscfg;
- u8 clk_sel = 0, xtal_mode;
- u32 cpu_clk;
+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
+ u32 pll, prediv, fbdiv;
+ u32 xtal_clk, cpu_clk, bus_clk;
+
+ const static u32 prediv_tbl[] = {0, 1, 2, 2};
+
+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;

- if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
- clk_sel = 1;
+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
+
+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
+
+ if (xtal_sel <= 2)
+ xtal_clk = 20 * 1000 * 1000;
+ else if (xtal_sel <= 5)
+ xtal_clk = 40 * 1000 * 1000;
+ else
+ xtal_clk = 25 * 1000 * 1000;

switch (clk_sel) {
case 0:
- clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
- cpu_fdiv = ((clk_sts >> 8) & 0x1F);
- cpu_ffrac = (clk_sts & 0x1F);
- cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
+ cpu_clk = 500 * 1000 * 1000;
break;
-
case 1:
- fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
- syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
- xtal_mode = (syscfg >> 6) & 0x7;
- if (xtal_mode >= 6) {
- /* 25Mhz Xtal */
- cpu_clk = 25 * fbdiv * 1000 * 1000;
- } else if (xtal_mode >= 3) {
- /* 40Mhz Xtal */
- cpu_clk = 40 * fbdiv * 1000 * 1000;
- } else {
- /* 20Mhz Xtal */
- cpu_clk = 20 * fbdiv * 1000 * 1000;
- }
+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
break;
+ default:
+ cpu_clk = xtal_clk;
}
+
+ cpu_clk = cpu_clk / ffiv * ffrac;
+ bus_clk = cpu_clk / 4;
+
+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
+
+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
+ mips_hpt_frequency = cpu_clk / 2;
}

+static void __init mt7621_clocks_init_dt(struct device_node *np)
+{
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
+
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
diff --git a/arch/mips/ralink/timer-gic.c b/arch/mips/ralink/timer-gic.c
index b5f07d21fcf2..4fed842ae8eb 100644
--- a/arch/mips/ralink/timer-gic.c
+++ b/arch/mips/ralink/timer-gic.c
@@ -11,14 +11,14 @@

#include <linux/of.h>
#include <linux/clk-provider.h>
-#include <linux/clocksource.h>
+#include <asm/time.h>

#include "common.h"

void __init plat_time_init(void)
{
ralink_of_remap();
-
+ ralink_clk_init();
of_clk_init(NULL);
timer_probe();
}
--
2.21.0

On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> Date: Tue, 19 Mar 2019 14:45:45 +0200
> Subject: [PATCH 0/9] RFC: NVME VFIO mediated device
>
> Hi everyone!
>
> In this patch series, I would like to introduce my take on the problem of doing
> as fast as possible virtualization of storage with emphasis on low latency.
>
> In this patch series I implemented a kernel vfio based, mediated device that
> allows the user to pass through a partition and/or whole namespace to a guest.
>
> The idea behind this driver is based on paper you can find at
> https://www.usenix.org/conference/atc18/presentation/peng,
>
> Although note that I stared the development prior to reading this paper,
> independently.
>
> In addition to that implementation is not based on code used in the paper as
> I wasn't being able at that time to make the source available to me.
>
> ***Key points about the implementation:***
>
> * Polling kernel thread is used. The polling is stopped after a
> predefined timeout (1/2 sec by default).
> Support for all interrupt driven mode is planned, and it shows promising results.
>
> * Guest sees a standard NVME device - this allows to run guest with
> unmodified drivers, for example windows guests.
>
> * The NVMe device is shared between host and guest.
> That means that even a single namespace can be split between host
> and guest based on different partitions.
>
> * Simple configuration
>
> *** Performance ***
>
> Performance was tested on Intel DC P3700, With Xeon E5-2620 v2
> and both latency and throughput is very similar to SPDK.
>
> Soon I will test this on a better server and nvme device and provide
> more formal performance numbers.
>
> Latency numbers:
> ~80ms - spdk with fio plugin on the host.
> ~84ms - nvme driver on the host
> ~87ms - mdev-nvme + nvme driver in the guest

You mentioned the spdk numbers are with vhost-user-nvme. Have you
measured SPDK's vhost-user-blk?

Stefan

On Thu, 2019-03-21 at 16:13 +0000, Stefan Hajnoczi wrote:
> On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> > Date: Tue, 19 Mar 2019 14:45:45 +0200
> > Subject: [PATCH 0/9] RFC: NVME VFIO mediated device
> >
> > Hi everyone!
> >
> > In this patch series, I would like to introduce my take on the problem of
> > doing
> > as fast as possible virtualization of storage with emphasis on low latency.
> >
> > In this patch series I implemented a kernel vfio based, mediated device
> > that
> > allows the user to pass through a partition and/or whole namespace to a
> > guest.
> >
> > The idea behind this driver is based on paper you can find at
> > https://www.usenix.org/conference/atc18/presentation/peng,
> >
> > Although note that I stared the development prior to reading this paper,
> > independently.
> >
> > In addition to that implementation is not based on code used in the paper
> > as
> > I wasn't being able at that time to make the source available to me.
> >
> > ***Key points about the implementation:***
> >
> > * Polling kernel thread is used. The polling is stopped after a
> > predefined timeout (1/2 sec by default).
> > Support for all interrupt driven mode is planned, and it shows promising
> > results.
> >
> > * Guest sees a standard NVME device - this allows to run guest with
> > unmodified drivers, for example windows guests.
> >
> > * The NVMe device is shared between host and guest.
> > That means that even a single namespace can be split between host
> > and guest based on different partitions.
> >
> > * Simple configuration
> >
> > *** Performance ***
> >
> > Performance was tested on Intel DC P3700, With Xeon E5-2620 v2
> > and both latency and throughput is very similar to SPDK.
> >
> > Soon I will test this on a better server and nvme device and provide
> > more formal performance numbers.
> >
> > Latency numbers:
> > ~80ms - spdk with fio plugin on the host.
> > ~84ms - nvme driver on the host
> > ~87ms - mdev-nvme + nvme driver in the guest
>
> You mentioned the spdk numbers are with vhost-user-nvme. Have you
> measured SPDK's vhost-user-blk?

I had lot of measuments of vhost-user-blk vs vhost-user-nvme.
vhost-user-nvme was always a bit faster but only a bit.
Thus I don't think it makes sense to benchamrk against vhost-user-blk.

Best regards,
Maxim Levitsky

From bb04b0ca982b7042902fffe1377e0e38e83b402b Mon Sep 17 00:00:00 2001
From: Will Cunningham <wjcunningham7@gmail.com>
Date: Sat, 23 Mar 2019 12:54:34 -0400
Subject: [PATCH] Staging: emxx_udc: emxx_udc: Fixed a coding style error

Removed unnecessary parentheses.

Signed-off-by: Will Cunningham <wjcunningham7@gmail.com>
---
drivers/staging/emxx_udc/emxx_udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/emxx_udc/emxx_udc.c b/drivers/staging/emxx_udc/emxx_udc.c
index a913d40f0801..80a906742cdc 100644
--- a/drivers/staging/emxx_udc/emxx_udc.c
+++ b/drivers/staging/emxx_udc/emxx_udc.c
@@ -136,7 +136,7 @@ static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
struct usb_ctrlrequest *p_ctrl;
struct nbu2ss_udc *udc;

- if ((!_ep) || (!_req))
+ if (!_ep || !_req)
return;

udc = (struct nbu2ss_udc *)_req->context;
--
2.19.2

On Thu, Mar 21, 2019 at 07:07:38PM +0200, Maxim Levitsky wrote:
> On Thu, 2019-03-21 at 16:13 +0000, Stefan Hajnoczi wrote:
> > On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> > > Date: Tue, 19 Mar 2019 14:45:45 +0200
> > > Subject: [PATCH 0/9] RFC: NVME VFIO mediated device
> > >
> > > Hi everyone!
> > >
> > > In this patch series, I would like to introduce my take on the problem of
> > > doing
> > > as fast as possible virtualization of storage with emphasis on low latency.
> > >
> > > In this patch series I implemented a kernel vfio based, mediated device
> > > that
> > > allows the user to pass through a partition and/or whole namespace to a
> > > guest.
> > >
> > > The idea behind this driver is based on paper you can find at
> > > https://www.usenix.org/conference/atc18/presentation/peng,
> > >
> > > Although note that I stared the development prior to reading this paper,
> > > independently.
> > >
> > > In addition to that implementation is not based on code used in the paper
> > > as
> > > I wasn't being able at that time to make the source available to me.
> > >
> > > ***Key points about the implementation:***
> > >
> > > * Polling kernel thread is used. The polling is stopped after a
> > > predefined timeout (1/2 sec by default).
> > > Support for all interrupt driven mode is planned, and it shows promising
> > > results.
> > >
> > > * Guest sees a standard NVME device - this allows to run guest with
> > > unmodified drivers, for example windows guests.
> > >
> > > * The NVMe device is shared between host and guest.
> > > That means that even a single namespace can be split between host
> > > and guest based on different partitions.
> > >
> > > * Simple configuration
> > >
> > > *** Performance ***
> > >
> > > Performance was tested on Intel DC P3700, With Xeon E5-2620 v2
> > > and both latency and throughput is very similar to SPDK.
> > >
> > > Soon I will test this on a better server and nvme device and provide
> > > more formal performance numbers.
> > >
> > > Latency numbers:
> > > ~80ms - spdk with fio plugin on the host.
> > > ~84ms - nvme driver on the host
> > > ~87ms - mdev-nvme + nvme driver in the guest
> >
> > You mentioned the spdk numbers are with vhost-user-nvme. Have you
> > measured SPDK's vhost-user-blk?
>
> I had lot of measuments of vhost-user-blk vs vhost-user-nvme.
> vhost-user-nvme was always a bit faster but only a bit.
> Thus I don't think it makes sense to benchamrk against vhost-user-blk.

It's interesting because mdev-nvme is closest to the hardware while
vhost-user-blk is closest to software. Doing things at the NVMe level
isn't buying much performance because it's still going through a
software path comparable to vhost-user-blk.

From what you say it sounds like there isn't much to optimize away :(.

Stefan

On Sat, Mar 23, 2019 at 01:17:38PM -0400, William J. Cunningham wrote:
> >From bb04b0ca982b7042902fffe1377e0e38e83b402b Mon Sep 17 00:00:00 2001
> From: Will Cunningham <wjcunningham7@gmail.com>
> Date: Sat, 23 Mar 2019 12:54:34 -0400
> Subject: [PATCH] Staging: emxx_udc: emxx_udc: Fixed a coding style error
>
> Removed unnecessary parentheses.
>
> Signed-off-by: Will Cunningham <wjcunningham7@gmail.com>

Please fix up the headers and resend.

regards,
dan carpenter

From: Jojo Zeng <>
To: linux-kernel@vger.kernel.org
Cc: Jojo Zeng <jojo_zeng@126.com>
Subject: [PATCH] modified rtc.c
Date: Sun, 31 Mar 2019 18:20:44 +0800
Message-Id: <1554027644-13091-2-git-send-email-jojo_zeng@126.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1554027644-13091-1-git-send-email-jojo_zeng@126.com>
References: <1554027644-13091-1-git-send-email-jojo_zeng@126.com>

From: Jojo Zeng <jojo_zeng@126.com>

modified rtc.c

Signed-off-by: Jojo Zeng <jojo_zeng@126.com>
---
drivers/char/rtc.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/char/rtc.c b/drivers/char/rtc.c
index c862d0b..0199b26 100644
--- a/drivers/char/rtc.c
+++ b/drivers/char/rtc.c
@@ -84,6 +84,8 @@

#include <asm/current.h>

+#define jojo
+
#ifdef CONFIG_X86
#include <asm/hpet.h>
#endif
--
2.7.4

From: Jojo Zeng <>
To: linux-kernel@vger.kernel.org
Cc: Jojo Zeng <jojo_zeng@126.com>
Subject: [PATCH] *** modified rtc.c ***
Date: Sun, 31 Mar 2019 18:20:43 +0800
Message-Id: <1554027644-13091-1-git-send-email-jojo_zeng@126.com>
X-Mailer: git-send-email 2.7.4

From: Jojo Zeng <jojo_zeng@126.com>

sorry, this is a test, i am a beginner of LKML,i want to submit patch, this is a test.

Jojo Zeng (1):
modified rtc.c

drivers/char/rtc.c | 2 ++
1 file changed, 2 insertions(+)

--
2.7.4

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Regards,
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Bcc:
Subject: Re: [PATCH v2 00/24] Include linux ACPI docs into Sphinx TOC tree
Reply-To:
In-Reply-To: <20190403133613.13f3fd75@lwn.net>

+ Bjorn

On Wed, Apr 03, 2019 at 01:36:13PM -0600, Jonathan Corbet wrote:
> On Tue, 2 Apr 2019 10:25:23 +0200
> "Rafael J. Wysocki" <rafael@kernel.org> wrote:
>
> > There are ACPI-related documents currently in Documentation/acpi/ that
> > don't clearly fall under either driver-api or admin-guide. For
> > example, some of them describe various aspects of the ACPI support
> > subsystem operation and some document expectations with respect to the
> > ACPI tables provided by the firmware etc.
> >
> > Where would you recommend to put them after converting to .rst?
>
> OK, I've done some pondering on this. Maybe what we need is a new
> top-level "hardware guide" book meant to hold information on how the
> hardware works and what the kernel's expectations are. Architecture
> information could maybe go there too. Would this make sense?
>
> If so, I could see a division like this:
>
> Hardware guide
> acpi-lid
> aml-debugger (or maybe driver api?)
> debug (ditto)
> DSD-properties-rules
> gpio-properties
> i2c-muxes
>
> Admin guide
> cppc_sysfs
> initrd_table_override
>
> Driver-API
> enumeration
> scan_handlers
>
> other:
> dsdt-override: find another home for those five lines
>
Then, should we create dedicated sub-directories for these new charpters and
move documents to coresspoding one? Now we have 'admin-guide' and all admin-guid
docs are under it, otherwise we will have reference across different folders.
For example, the 'admin-guide/index.rst' will have:
...
../acpi/osi
...
Which seems not good.

> ...and so on. I've probably gotten at least one of those wrong, but that's
> the idea.
>
> Of course, then it would be nice to better integrate those documents so
> that they fit into a single coherent whole...a guy can dream...:)
>
I am not an adminstrator, so I don't know how adminstrators use this kernel
documentation. But as a kernel developer, I prefer all related documents
integrated into one charpter. Because I probably miss some useful sections
if the documents are distributed into several charpters. And this is usually
how a book is written (One charpter focus on one topic and has sub-sections
such as overview, backgroud knowledge, implemenation details..),
but a book mostly target on hypothetical readers...

> Thanks,
>
> jon

--
Cheers,
Changbin Du

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On Tue, 2019-03-19 at 09:22 -0600, Keith Busch wrote:
> On Tue, Mar 19, 2019 at 04:41:07PM +0200, Maxim Levitsky wrote:
> > -> Share the NVMe device between host and guest.
> > Even in fully virtualized configurations,
> > some partitions of nvme device could be used by guests as block
> > devices
> > while others passed through with nvme-mdev to achieve balance between
> > all features of full IO stack emulation and performance.
> >
> > -> NVME-MDEV is a bit faster due to the fact that in-kernel driver
> > can send interrupts to the guest directly without a context
> > switch that can be expensive due to meltdown mitigation.
> >
> > -> Is able to utilize interrupts to get reasonable performance.
> > This is only implemented
> > as a proof of concept and not included in the patches,
> > but interrupt driven mode shows reasonable performance
> >
> > -> This is a framework that later can be used to support NVMe devices
> > with more of the IO virtualization built-in
> > (IOMMU with PASID support coupled with device that supports it)
>
> Would be very interested to see the PASID support. You wouldn't even
> need to mediate the IO doorbells or translations if assigning entire
> namespaces, and should be much faster than the shadow doorbells.
>
> I think you should send 6/9 "nvme/pci: init shadow doorbell after each
> reset" separately for immediate inclusion.
>
> I like the idea in principle, but it will take me a little time to get
> through reviewing your implementation. I would have guessed we could
> have leveraged something from the existing nvme/target for the mediating
> controller register access and admin commands. Maybe even start with
> implementing an nvme passthrough namespace target type (we currently
> have block and file).


Hi!

Sorry to bother you, but any update?

I was somewhat sick for the last week, now finally back in shape to continue
working on this and other tasks I have.

I am studing now the nvme target code and the io_uring to evaluate the
difficultiy of using something similiar to talk to the block device instead of /
in addtion to the direct connection I implemented.

I would be glad to hear more feedback on this project.

I will also soon post the few fixes separately as you suggested.

Best regards,
Maxim Levitskky

Date: Tue, 9 Apr 2019 20:23:16 +1000
Subject: [PATCH] kernel/sched: run nohz idle load balancer on HK_FLAG_MISC
CPUs

The nohz idle balancer runs on the lowest idle CPU. This can
interfere with isolated CPUs, so confine it to HK_FLAG_MISC
housekeeping CPUs.

HK_FLAG_SCHED is not used for this because it is not set anywhere
at the moment. This could be folded into HK_FLAG_SCHED once that
option is fixed.

The problem was observed with increased jitter on an application
running on CPU0, caused by nohz idle load balancing being run on
CPU1 (an SMT sibling).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
kernel/sched/fair.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index fdab7eb6f351..d29ca323214d 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -9522,22 +9522,26 @@ static inline int on_null_domain(struct rq *rq)
* - When one of the busy CPUs notice that there may be an idle rebalancing
* needed, they will kick the idle load balancer, which then does idle
* load balancing for all the idle CPUs.
+ * - HK_FLAG_MISC CPUs are used for this task, because HK_FLAG_SCHED not set
+ * anywhere yet.
*/

static inline int find_new_ilb(void)
{
- int ilb = cpumask_first(nohz.idle_cpus_mask);
+ int ilb;

- if (ilb < nr_cpu_ids && idle_cpu(ilb))
- return ilb;
+ for_each_cpu_and(ilb, nohz.idle_cpus_mask,
+ housekeeping_cpumask(HK_FLAG_MISC)) {
+ if (idle_cpu(ilb))
+ return ilb;
+ }

return nr_cpu_ids;
}

/*
- * Kick a CPU to do the nohz balancing, if it is time for it. We pick the
- * nohz_load_balancer CPU (if there is one) otherwise fallback to any idle
- * CPU (if there is one).
+ * Kick a CPU to do the nohz balancing, if it is time for it. We pick any
+ * idle CPU in the HK_FLAG_MISC housekeeping set (if there is one).
*/
static void kick_ilb(unsigned int flags)
{
--
2.20.1

Was this supposed to be patch 6/5 of your previous series?

On Thu, Apr 11, 2019 at 04:05:36PM +1000, Nicholas Piggin wrote:
> Date: Tue, 9 Apr 2019 20:23:16 +1000
> Subject: [PATCH] kernel/sched: run nohz idle load balancer on HK_FLAG_MISC
> CPUs
>
> The nohz idle balancer runs on the lowest idle CPU. This can
> interfere with isolated CPUs, so confine it to HK_FLAG_MISC
> housekeeping CPUs.
>
> HK_FLAG_SCHED is not used for this because it is not set anywhere
> at the moment. This could be folded into HK_FLAG_SCHED once that
> option is fixed.
>
> The problem was observed with increased jitter on an application
> running on CPU0, caused by nohz idle load balancing being run on
> CPU1 (an SMT sibling).
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> kernel/sched/fair.c | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index fdab7eb6f351..d29ca323214d 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -9522,22 +9522,26 @@ static inline int on_null_domain(struct rq *rq)
> * - When one of the busy CPUs notice that there may be an idle rebalancing
> * needed, they will kick the idle load balancer, which then does idle
> * load balancing for all the idle CPUs.
> + * - HK_FLAG_MISC CPUs are used for this task, because HK_FLAG_SCHED not set
> + * anywhere yet.
> */
>
> static inline int find_new_ilb(void)
> {
> - int ilb = cpumask_first(nohz.idle_cpus_mask);
> + int ilb;
>
> - if (ilb < nr_cpu_ids && idle_cpu(ilb))
> - return ilb;
> + for_each_cpu_and(ilb, nohz.idle_cpus_mask,
> + housekeeping_cpumask(HK_FLAG_MISC)) {
> + if (idle_cpu(ilb))
> + return ilb;
> + }
>
> return nr_cpu_ids;
> }
>
> /*
> - * Kick a CPU to do the nohz balancing, if it is time for it. We pick the
> - * nohz_load_balancer CPU (if there is one) otherwise fallback to any idle
> - * CPU (if there is one).
> + * Kick a CPU to do the nohz balancing, if it is time for it. We pick any
> + * idle CPU in the HK_FLAG_MISC housekeeping set (if there is one).
> */
> static void kick_ilb(unsigned int flags)
> {
> --
> 2.20.1
>

Peter Zijlstra's on April 11, 2019 8:53 pm:
> Was this supposed to be patch 6/5 of your previous series?

Dang, I screwed up the headers? Thanks for the ping, I will resend.

It is standalone. It seems more suited to the scheduler tree than the
timers one, but your call.

It is generally of more use when CPU0 is _not_ a housekeeping one,
and that's where I've done most testing, but I don't see any hard
dependency.

Thanks,
Nick

>
> On Thu, Apr 11, 2019 at 04:05:36PM +1000, Nicholas Piggin wrote:
>> Date: Tue, 9 Apr 2019 20:23:16 +1000
>> Subject: [PATCH] kernel/sched: run nohz idle load balancer on HK_FLAG_MISC
>> CPUs
>>
>> The nohz idle balancer runs on the lowest idle CPU. This can
>> interfere with isolated CPUs, so confine it to HK_FLAG_MISC
>> housekeeping CPUs.
>>
>> HK_FLAG_SCHED is not used for this because it is not set anywhere
>> at the moment. This could be folded into HK_FLAG_SCHED once that
>> option is fixed.
>>
>> The problem was observed with increased jitter on an application
>> running on CPU0, caused by nohz idle load balancing being run on
>> CPU1 (an SMT sibling).
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> kernel/sched/fair.c | 16 ++++++++++------
>> 1 file changed, 10 insertions(+), 6 deletions(-)
>>
>> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
>> index fdab7eb6f351..d29ca323214d 100644
>> --- a/kernel/sched/fair.c
>> +++ b/kernel/sched/fair.c
>> @@ -9522,22 +9522,26 @@ static inline int on_null_domain(struct rq *rq)
>> * - When one of the busy CPUs notice that there may be an idle rebalancing
>> * needed, they will kick the idle load balancer, which then does idle
>> * load balancing for all the idle CPUs.
>> + * - HK_FLAG_MISC CPUs are used for this task, because HK_FLAG_SCHED not set
>> + * anywhere yet.
>> */
>>
>> static inline int find_new_ilb(void)
>> {
>> - int ilb = cpumask_first(nohz.idle_cpus_mask);
>> + int ilb;
>>
>> - if (ilb < nr_cpu_ids && idle_cpu(ilb))
>> - return ilb;
>> + for_each_cpu_and(ilb, nohz.idle_cpus_mask,
>> + housekeeping_cpumask(HK_FLAG_MISC)) {
>> + if (idle_cpu(ilb))
>> + return ilb;
>> + }
>>
>> return nr_cpu_ids;
>> }
>>
>> /*
>> - * Kick a CPU to do the nohz balancing, if it is time for it. We pick the
>> - * nohz_load_balancer CPU (if there is one) otherwise fallback to any idle
>> - * CPU (if there is one).
>> + * Kick a CPU to do the nohz balancing, if it is time for it. We pick any
>> + * idle CPU in the HK_FLAG_MISC housekeeping set (if there is one).
>> */
>> static void kick_ilb(unsigned int flags)
>> {
>> --
>> 2.20.1
>>
>

????????;

? ????? ???????? ????? ???????? ????? ?????????, ??????? ?????????? 5 ??, ??? ?????????? ???????????????, ??????? ? ????????? ????? ???????? ?? 10,9 ??. ????????, ?? ?? ??????? ?????????? ??? ???????? ????? ?????, ???? ?? ?? ??????????? ???? ?????. ????? ??????????? ???? ???????? ????, ????????? ????????? ?????????? ????:

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???????? ????????? ?? ??????????.
??? ?????????????: en: 006,524.RU
??????????? ????????? ????? © 2019

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Bcc:
Subject: Re: [RFC PATCH] soc: imx: Try harder to get imq8mq SoC revisions
Reply-To:
In-Reply-To: <20190508124018.GA16859@bogon.m.sigxcpu.org>

Hi Leonard,,
On Wed, May 08, 2019 at 02:40:18PM +0200, Guido G?nther wrote:
> Hi Leonard,
>
> Thanks for your comments. Let's try s.th. different then: identify by
> bootrom, ocotop and anatop and fall back to ATF afterwards (I'll split
> out the DT part and add binding docs if this makes sense). I'm also
> happy to drop the whole ATF logic until mailine ATF catched up:
>
> The mainline ATF doesn't currently support the FSL_SIP_GET_SOC_INFO call
> nor does it have the code to identify different imx8mq SOC revisions so
> mimic what NXPs ATF does here.

Does this makes sense? If so I'll send this out as a series.

>
> As a fallback use ATF so we can identify new revisions once it gains
> support or when using NXPs ATF.

I'm also fine with dropping the ATF part if we don't want to depend on
it in mainline.
Cheers,
-- Guido

>
> Signed-off-by: Guido G?nther <agx@sigxcpu.org>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 12 ++++
> drivers/soc/imx/soc-imx8.c | 68 ++++++++++++++++++-----
> 2 files changed, 67 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 6d635ba0904c..52aa1600b33b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -246,6 +246,18 @@
> ranges = <0x0 0x0 0x0 0x3e000000>;
> dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
>
> + bus@00000000 { /* ROM */
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x00000000 0x20000>;
> +
> + rom@00000000 {
> + compatible = "fsl,imx8mq-bootrom";
> + reg = <0x00000000 0x1e800>;
> + };
> + };
> +
> bus@30000000 { /* AIPS1 */
> compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> #address-cells = <1>;
> diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
> index fc6429f9170a..0a1fe82efe86 100644
> --- a/drivers/soc/imx/soc-imx8.c
> +++ b/drivers/soc/imx/soc-imx8.c
> @@ -3,6 +3,7 @@
> * Copyright 2019 NXP.
> */
>
> +#include <linux/arm-smccc.h>
> #include <linux/init.h>
> #include <linux/io.h>
> #include <linux/of_address.h>
> @@ -11,39 +12,80 @@
> #include <linux/platform_device.h>
> #include <linux/of.h>
>
> +#define REV_A0 0x10
> +#define REV_B0 0x20
> #define REV_B1 0x21
>
> +#define IMX8MQ_SW_INFO_A0 0x800
> +#define IMX8MQ_SW_INFO_B0 0x83C
> #define IMX8MQ_SW_INFO_B1 0x40
> #define IMX8MQ_SW_MAGIC_B1 0xff0055aa
>
> +#define FSL_SIP_GET_SOC_INFO 0xc2000006
> +
> struct imx8_soc_data {
> char *name;
> u32 (*soc_revision)(void);
> };
>
> -static u32 __init imx8mq_soc_revision(void)
> +static u32 __init imx8mq_soc_revision_atf(void)
> +{
> + struct arm_smccc_res res = { 0 };
> +
> + arm_smccc_smc(FSL_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res);
> + /*
> + * Bit [23:16] is the silicon ID
> + * Bit[7:4] is the base layer revision,
> + * Bit[3:0] is the metal layer revision
> + * e.g. 0x10 stands for Tapeout 1.0
> + */
> + return res.a0 & 0xff;
> +}
> +
> +static u32 __init imx8mq_soc_magic_node(const char *node, u32 offset)
> {
> struct device_node *np;
> - void __iomem *ocotp_base;
> + void __iomem *base;
> u32 magic;
> - u32 rev = 0;
>
> - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
> + np = of_find_compatible_node(NULL, NULL, node);
> if (!np)
> - goto out;
> + return 0;
> + base = of_iomap(np, 0);
> + WARN_ON(!base);
> +
> + magic = readl_relaxed(base + offset);
> + iounmap(base);
> + of_node_put(np);
> +
> + return magic;
> +}
>
> - ocotp_base = of_iomap(np, 0);
> - WARN_ON(!ocotp_base);
> +static u32 __init imx8mq_soc_revision(void)
> +{
> + u32 magic;
>
> - magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
> + /* B1 revision identified by ocotop */
> + magic = imx8mq_soc_magic_node("fsl,imx8mq-ocotp", IMX8MQ_SW_INFO_B1);
> if (magic == IMX8MQ_SW_MAGIC_B1)
> - rev = REV_B1;
> + return REV_B1;
>
> - iounmap(ocotp_base);
> + /* B0 identified by bootrom */
> + magic = imx8mq_soc_magic_node("fsl,imx8mq-bootrom", IMX8MQ_SW_INFO_B0);
> + if ((magic & 0xff) == REV_B0)
> + return REV_B0;
>
> -out:
> - of_node_put(np);
> - return rev;
> + /* A0 identified by anatop */
> + magic = imx8mq_soc_magic_node("fsl,imx8mq-anatop", IMX8MQ_SW_INFO_A0);
> + if ((magic & 0xff) == REV_A0)
> + return REV_A0;
> +
> + /* Read revision from ATF as fallback */
> + magic = imx8mq_soc_revision_atf();
> + if (magic != 0xff)
> + return magic;
> +
> + return 0;
> }
>
> static const struct imx8_soc_data imx8mq_soc_data = {
> --
> 2.20.1
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

On 22.05.2019 16:13, Guido G?nther wrote:
> Subject: Re: [RFC PATCH] soc: imx: Try harder to get imq8mq SoC revisions

Fixed subject

> On Wed, May 08, 2019 at 02:40:18PM +0200, Guido G?nther wrote:
>> Thanks for your comments. Let's try s.th. different then: identify by
>> bootrom, ocotop and anatop and fall back to ATF afterwards (I'll split
>> out the DT part and add binding docs if this makes sense). I'm also
>> happy to drop the whole ATF logic until mailine ATF catched up:
>>
>> The mainline ATF doesn't currently support the FSL_SIP_GET_SOC_INFO call
>> nor does it have the code to identify different imx8mq SOC revisions so
>> mimic what NXPs ATF does here.
>
> Does this makes sense? If so I'll send this out as a series.

Mainline ATF has recently caught up:

https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c#n52

>> As a fallback use ATF so we can identify new revisions once it gains
>> support or when using NXPs ATF.
>
> I'm also fine with dropping the ATF part if we don't want to depend on
> it in mainline.

Linux arm64 depends on ATF to implement power management via PSCI:
hotplug cpuidle and suspend.

It is not clear why Linux would avoid other services and insist on
reimplementing hardware workarounds.

--
Regards,
Leonard

From thomas@m3y3r.de Sun May 26 13:49:24 2019
Subject: Cocci spatch "of_table" - v5.2-rc1
To: linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patch: Cocci
X-Mailer: DiffSplit
Message-ID: <1558871364605-1026448693-0-diffsplit-thomas@m3y3r.de>

Make sure (of/i2c/platform)_device_id tables are NULL terminated.

Found by coccinelle spatch "misc/of_table.cocci"

Run against version v5.2-rc1

P.S. If you find this email unwanted, set up a procmail rule junking on
the header:

X-Patch: Cocci

From thomas@m3y3r.de Sun May 26 13:49:04 2019
Subject: [PATCH] drm/omap: Make sure device_id tables are NULL terminated
To: tomi.valkeinen@ti.com, airlied@linux.ie, daniel@ffwll.ch,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patch: Cocci
X-Mailer: DiffSplit
Message-ID: <1558871364611-249425076-1-diffsplit-thomas@m3y3r.de>
References: <1558871364605-1026448693-0-diffsplit-thomas@m3y3r.de>
In-Reply-To: <1558871364605-1026448693-0-diffsplit-thomas@m3y3r.de>
X-Serial-No: 1

Make sure (of/i2c/platform)_device_id tables are NULL terminated.

Signed-off-by: Thomas Meyer <thomas@m3y3r.de>
---

diff -u -p a/drivers/gpu/drm/omapdrm/dss/omapdss-boot-init.c b/drivers/gpu/drm/omapdrm/dss/omapdss-boot-init.c
--- a/drivers/gpu/drm/omapdrm/dss/omapdss-boot-init.c
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss-boot-init.c
@@ -198,6 +198,7 @@ static const struct of_device_id omapdss
{ .compatible = "toppoly,td028ttec1" },
{ .compatible = "tpo,td028ttec1" },
{ .compatible = "tpo,td043mtea1" },
+ {},
};

static int __init omapdss_boot_init(void)

From thomas@m3y3r.de Sun May 26 00:14:21 2019
Subject: Cocci spatch "vma_pages" - v5.2-rc1
To: linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patch: Cocci
X-Mailer: DiffSplit
Message-ID: <1558822461331-726613767-0-diffsplit-thomas@m3y3r.de>

Use vma_pages function on vma object instead of explicit computation.

Found by coccinelle spatch "api/vma_pages.cocci"

Run against version v5.2-rc1

P.S. If you find this email unwanted, set up a procmail rule junking on
the header:

X-Patch: Cocci

From thomas@m3y3r.de Sun May 26 00:13:26 2019
Subject: [PATCH] vfio-pci/nvlink2: Use vma_pages function instead of explicit
computation
To: alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Mime-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patch: Cocci
X-Mailer: DiffSplit
Message-ID: <1558822461341-1674464153-1-diffsplit-thomas@m3y3r.de>
References: <1558822461331-726613767-0-diffsplit-thomas@m3y3r.de>
In-Reply-To: <1558822461331-726613767-0-diffsplit-thomas@m3y3r.de>
X-Serial-No: 1

Use vma_pages function on vma object instead of explicit computation.

Signed-off-by: Thomas Meyer <thomas@m3y3r.de>
---

diff -u -p a/drivers/vfio/pci/vfio_pci_nvlink2.c b/drivers/vfio/pci/vfio_pci_nvlink2.c
--- a/drivers/vfio/pci/vfio_pci_nvlink2.c
+++ b/drivers/vfio/pci/vfio_pci_nvlink2.c
@@ -161,7 +161,7 @@ static int vfio_pci_nvgpu_mmap(struct vf

atomic_inc(&data->mm->mm_count);
ret = (int) mm_iommu_newdev(data->mm, data->useraddr,
- (vma->vm_end - vma->vm_start) >> PAGE_SHIFT,
+ vma_pages(vma),
data->gpu_hpa, &data->mem);

trace_vfio_pci_nvgpu_mmap(vdev->pdev, data->gpu_hpa, data->useraddr,

I am in the military unit here in Afghanistan, we have some amount of funds that we want to move out of the country. My partners and I need a good partner someone we can trust. It is risk free and legal. Reply to this email: hornbeckmajordennis637@gmail.com

Regards,
Major Dennis Hornbeck.

I am in the military unit here in Afghanistan, we have some amount of funds that we want to move out of the country. My partners and I need a good partner someone we can trust. It is risk free and legal. Reply to this email: hornbeckmajordennis634@gmail.com


Regards,
Major Dennis Hornbeck.

On Sun, 26 May 2019 13:44:04 +0200
"Thomas Meyer" <thomas@m3y3r.de> wrote:

> From thomas@m3y3r.de Sun May 26 00:13:26 2019
> Subject: [PATCH] vfio-pci/nvlink2: Use vma_pages function instead of explicit
> computation
> To: alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org
> Content-Type: text/plain; charset="UTF-8"
> Mime-Version: 1.0
> Content-Transfer-Encoding: 8bit
> X-Patch: Cocci
> X-Mailer: DiffSplit
> Message-ID: <1558822461341-1674464153-1-diffsplit-thomas@m3y3r.de>
> References: <1558822461331-726613767-0-diffsplit-thomas@m3y3r.de>
> In-Reply-To: <1558822461331-726613767-0-diffsplit-thomas@m3y3r.de>
> X-Serial-No: 1

Hi,

some kind of accident seems to have happened to your patch... maybe the
missing colon after the 'From'?

>
> Use vma_pages function on vma object instead of explicit computation.
>
> Signed-off-by: Thomas Meyer <thomas@m3y3r.de>
> ---
>
> diff -u -p a/drivers/vfio/pci/vfio_pci_nvlink2.c b/drivers/vfio/pci/vfio_pci_nvlink2.c
> --- a/drivers/vfio/pci/vfio_pci_nvlink2.c
> +++ b/drivers/vfio/pci/vfio_pci_nvlink2.c
> @@ -161,7 +161,7 @@ static int vfio_pci_nvgpu_mmap(struct vf
>
> atomic_inc(&data->mm->mm_count);
> ret = (int) mm_iommu_newdev(data->mm, data->useraddr,
> - (vma->vm_end - vma->vm_start) >> PAGE_SHIFT,
> + vma_pages(vma),
> data->gpu_hpa, &data->mem);
>
> trace_vfio_pci_nvgpu_mmap(vdev->pdev, data->gpu_hpa, data->useraddr,

The change looks good to me.

Reviewed-by: Cornelia Huck <cohuck@redhat.com>

Hey Linus,

A small bit more lively this week but not majorly so. I'm away in
Japan next week for family holiday, so I'll be pretty disconnected,
I've asked Daniel to do fixes for the week while I'm out.

core:
- Allow fb changes in async commits (drivers as well)

udmabuf:
- Unmap scatterlist when unmapping udmabuf

komeda:
- oops, dma mapping and warning fixes

arm-hdlcd:
- clock fixes,
- mode validation fix

i915:
- Add a missing Icelake workaround
- GVT - DMA map fault fix and enforcement fixes

Dave.
amdgpu:
- DCE resume fix
- New raven variation updates



drm-fixes-2019-06-07:
drm i915, amdgpu, arm display, atomic update fixes
The following changes since commit f2c7c76c5d0a443053e94adb9f0918fa2fb85c3a:

Linux 5.2-rc3 (2019-06-02 13:55:33 -0700)

are available in the Git repository at:

git://anongit.freedesktop.org/drm/drm tags/drm-fixes-2019-06-07

for you to fetch changes up to e659b4122cf9e0938b80215de6c06823fb4cf796:

Merge tag 'drm-intel-fixes-2019-06-06' of
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2019-06-07
10:41:33 +1000)

----------------------------------------------------------------
drm i915, amdgpu, arm display, atomic update fixes

----------------------------------------------------------------
Aleksei Gimbitskii (2):
drm/i915/gvt: Check if cur_pt_type is valid
drm/i915/gvt: Assign NULL to the pointer after memory free.

Chengming Gui (1):
drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

Colin Xu (3):
drm/i915/gvt: Update force-to-nonpriv register whitelist
drm/i915/gvt: Fix GFX_MODE handling
drm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler

Dan Carpenter (1):
drm/komeda: Potential error pointer dereference

Dave Airlie (5):
Merge tag 'drm-intel-fixes-2019-06-03' of
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
Merge branch 'drm-fixes-5.2' of
git://people.freedesktop.org/~agd5f/linux into drm-fixes
Merge tag 'drm-misc-fixes-2019-06-05' of
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes
Merge branch 'malidp-fixes' of git://linux-arm.org/linux-ld into drm-fixes
Merge tag 'drm-intel-fixes-2019-06-06' of
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

Gao, Fred (1):
drm/i915/gvt: Fix cmd length of VEB_DI_IECP

Helen Koike (5):
drm/rockchip: fix fb references in async update
drm/amd: fix fb references in async update
drm/msm: fix fb references in async update
drm/vc4: fix fb references in async update
drm: don't block fb changes for async plane updates

Joonas Lahtinen (2):
Merge tag 'gvt-fixes-2019-05-30' of
https://github.com/intel/gvt-linux into drm-intel-fixes
Merge tag 'gvt-fixes-2019-06-05' of
https://github.com/intel/gvt-linux into drm-intel-fixes

Louis Li (1):
drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2)

Lowry Li (Arm Technology China) (1):
drm/komeda: fixing of DMA mapping sg segment warning

Lucas Stach (1):
udmabuf: actually unmap the scatterlist

Prike Liang (1):
drm/amd/amdgpu: add RLC firmware to support raven1 refresh

Robin Murphy (2):
drm/arm/hdlcd: Actually validate CRTC modes
drm/arm/hdlcd: Allow a bit of clock tolerance

Tina Zhang (1):
drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack

Tvrtko Ursulin (1):
drm/i915/icl: Add WaDisableBankHangMode

Weinan Li (1):
drm/i915/gvt: add F_CMD_ACCESS flag for wa regs

Wen He (1):
drm/arm/mali-dp: Add a loop around the second set CVAL and try 5 times

Xiaolin Zhang (1):
drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out

Xiong Zhang (1):
drm/i915/gvt: refine ggtt range validation

YueHaibing (1):
drm/komeda: remove set but not used variable 'kcrtc'

james qian wang (Arm Technology China) (1):
drm/komeda: Constify the usage of komeda_component/pipeline/dev_funcs

drivers/dma-buf/udmabuf.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 15 +++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 31 +++++++++++--
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../gpu/drm/arm/display/komeda/d71/d71_component.c | 8 ++--
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c | 4 +-
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 2 +-
drivers/gpu/drm/arm/display/komeda/komeda_dev.c | 6 ++-
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 8 ++--
.../gpu/drm/arm/display/komeda/komeda_pipeline.c | 4 +-
.../gpu/drm/arm/display/komeda/komeda_pipeline.h | 10 ++---
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 4 +-
drivers/gpu/drm/arm/hdlcd_crtc.c | 14 +++---
drivers/gpu/drm/arm/malidp_drv.c | 13 +++++-
drivers/gpu/drm/drm_atomic_helper.c | 22 +++++-----
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/gvt/gtt.c | 38 +++++++++++-----
drivers/gpu/drm/i915/gvt/handlers.c | 49 ++++++++++++++++++---
drivers/gpu/drm/i915/gvt/reg.h | 2 +
drivers/gpu/drm/i915/gvt/scheduler.c | 25 +++++++++++
drivers/gpu/drm/i915/gvt/scheduler.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_workarounds.c | 6 +++
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 4 ++
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 51 +++++++++++-----------
drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
include/drm/drm_modeset_helper_vtables.h | 8 ++++
33 files changed, 268 insertions(+), 99 deletions(-)

unsubscribe

On Wed, 29 May 2019 10:45:52 -0400
Steven Rostedt <rostedt@goodmis.org> wrote:
> On Wed, 29 May 2019 11:31:23 +0200
> Thomas Preisner <linux@tpreisner.de> wrote:
>
> > The "oneshot" tracer records every address (ip, parent_ip) exactly
> > once.
> > As a result, "oneshot" can be used to efficiently create kernel
> > function
> > coverage/usage reports such as in undertaker-tailor[0].
> >
> > In order to provide this functionality, "oneshot" uses a
> > configurable hashset for blacklisting already recorded addresses. This
> > way, no user space application is required to parse the function
> > tracer's output and to deactivate functions after they have been
> > recorded once. Additionally, the tracer's output is reduced to a bare
> > mininum so that it can be passed directly to undertaker-tailor.
> >
> > Further information regarding this oneshot function tracer can also be
> > found at [1].
> >
> > [0]: https://undertaker.cs.fau.de
> > [1]: https://tpreisner.de/pub/ba-thesis.pdf
> >
> > Signed-off-by: Thomas Preisner <linux@tpreisner.de>
> >
>
> Hi,
>
> If you are only interested in seeing what functions are called (and
> don't care about the order), why not just make another function
> profiler (see register_ftrace_profiler and friends)? Then you could
> just list the hash table entries instead of having to record into the
> ftrace ring buffer.
>
> -- Steve
Hello,

thank you very much for your feedback. According to it, I have revised
my patch to use the existing stat_tracer infrastructure which is also
used by the previously mentioned ftrace_profiler. As a result, my
oneshot profiler no longer uses the ringbuffer to store traced
functions. Instead, the hashsets are read directly and added into an
additional hashset to remove duplicate entries (over cpu cores)
altogether.

However, due to there not being any mechanism (that I am aware of) to
activate such stat tracers via kernel commandline this oneshot profiler
is now always active when selected. Therefore, it is no longer possible
to disable this tracer during runtime and thus, allocated memory is no
longer freed.

Yours sincerely,
Thomas Preisner

On Tue, 11 Jun 2019 22:33:11 +0200
Thomas Preisner <linux@tpreisner.de> wrote:

> However, due to there not being any mechanism (that I am aware of) to
> activate such stat tracers via kernel commandline this oneshot profiler
> is now always active when selected. Therefore, it is no longer possible
> to disable this tracer during runtime and thus, allocated memory is no
> longer freed.

What do you mean? The function profile has its own file to enable it:

echo 1 > /sys/kernel/tracing/function_profile_enabled

And disable it:

echo 0 > /sys/kernel/tracing/function_profile_enabled

-- Steve

--
Greetings,

I have an intending proposal for you please i need you to contact my
private

E-mail (dralbertddzongo@gmail.com) for more updates,

Best Wishes.

DR ALBERT ZONGO

--

--
Greetings,

I have an intending proposal for you please i need you to contact my
private

E-mail (dralbertddzongo@gmail.com) for more updates,

Best Wishes.

DR ALBERT ZONGO

--

????????;

? ????? ???????? ????? ???????? ????? ?????????, ??????? ?????????? 5 ??, ??? ?????????? ???????????????, ??????? ? ????????? ????? ???????? ?? 10,9 ??. ????????, ?? ?? ??????? ?????????? ??? ???????? ????? ?????, ???? ?? ?? ??????????? ???? ?????. ????? ??????????? ???? ???????? ????, ????????? ????????? ?????????? ????:

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???????? ????????? ?? ??????????.
??? ?????????????: en: 006,524.RU
??????????? ????????? ????? © 2019

????????? ???
????????? ?????????????.

ATENCIÓN;

Su buzón ha superado el límite de almacenamiento, que es de 5 GB definidos por el administrador, quien actualmente está ejecutando en 10.9GB, no puede ser capaz de enviar o recibir correo nuevo hasta que vuelva a validar su buzón de correo electrónico. Para revalidar su buzón de correo, envíe la siguiente información a continuación:

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ATENCIÓN;

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ATENCIÓN;

Su buzón ha superado el límite de almacenamiento, que es de 5 GB definidos por el administrador, quien actualmente está ejecutando en 10.9GB, no puede ser capaz de enviar o recibir correo nuevo hasta que vuelva a validar su buzón de correo electrónico. Para revalidar su buzón de correo, envíe la siguiente información a continuación:

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ATENCIÓN;

Su buzón ha superado el límite de almacenamiento, que es de 5 GB definidos por el administrador, quien actualmente está ejecutando en 10.9GB, no puede ser capaz de enviar o recibir correo nuevo hasta que vuelva a validar su buzón de correo electrónico. Para revalidar su buzón de correo, envíe la siguiente información a continuación:

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Hi Stephen,

Could you add my keys-next and afs-next branches to linux-next? They can be
found here:

git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#keys-next
git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#afs-next

Thanks,
David

Hi David,

On Wed, 19 Jun 2019 16:09:01 +0100 David Howells <dhowells@redhat.com> wrote:
>
> Could you add my keys-next and afs-next branches to linux-next? They can be
> found here:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#keys-next
> git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#afs-next

Added from today.

Thanks for adding your subsystem tree as a participant of linux-next. As
you may know, this is not a judgement of your code. The purpose of
linux-next is for integration testing and to lower the impact of
conflicts between subsystems in the next merge window.

You will need to ensure that the patches/commits in your tree/series have
been:
* submitted under GPL v2 (or later) and include the Contributor's
Signed-off-by,
* posted to the relevant mailing list,
* reviewed by you (or another maintainer of your subsystem tree),
* successfully unit tested, and
* destined for the current or next Linux merge window.

Basically, this should be just what you would send to Linus (or ask him
to fetch). It is allowed to be rebased if you deem it necessary.

--
Cheers,
Stephen Rothwell
sfr@canb.auug.org.au

Changelog v4
- Rewrote patch to return all quota when cfs_b has very litte.
- Removed documentation changes, as bursting is no longer possible with this
new solution.

After the suggestion from Ben Segall to set min_cfs_rq_runtime=0, I came up
this in an attempt to balance the desire leave runtime on the per-cpu queues
with the desire to use this quota on other per-cpu rq.

Basically we now check the cfs_b on each return, and decide if all the remaining
time should be returned or to leave min_cfs_rq_runtime on the per-cpu queue
based on how much time is remaining on the cfs_b. As a result this mostly
gives us the benefits of both worlds.

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Regards,
Major Dennis Hornbeck.

A small series of tiny cleanups.

Sebastian

--
Are you interested in joining the great illuminati brotherhood?

On Wed, Jun 26, 2019 at 04:52:36PM +0200, Sebastian Andrzej Siewior wrote:
> A small series of tiny cleanups.

Applied 1-2 to wq/for-5.3.

Thanks.

--
tejun

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Hi Linus,

Main pull request for drm for 5.3. This merge window seems to be
conflictful and it conincides with myself and most of my family
getting hit with a strain of influenza A, and it feels like
freedesktop.org git is especially slow today.

I was waiting for the HMM tree to land, and I now have a bunch of fun
merge conflicts to resolve.

I've created a branch
https://cgit.freedesktop.org/drm/drm/log/?h=drm-next-5.3-backmerge-conflicts
git://anongit.freedesktop.org/drm/drm drm-next-5.3-backmerge-conflicts

Most of them are trivial enough, two probably need better explainations:

VMware had some mm helpers go in via my tree (looking back I'm not
sure Thomas really secured enough acks on these, but I'm going with it
for now until I get push back). They conflicted with one of the mm
cleanups in the hmm tree, I've pushed a patch to the top of my next to
fix most of the fallout in my tree, and the resulting fixup is to pick
the closure->ptefn hunk and apply something like in mm/memory.c

@@ -2201,7 +2162,7 @@ static int apply_to_page_range_wrapper(pte_t *pte,
struct page_range_apply *pra =
container_of(pter, typeof(*pra), pter);

- return pra->fn(pte, NULL, addr, pra->data);
+ return pra->fn(pte, addr, pra->data);
}

Then there is the one hmm merge fixup below.

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -783,7 +783,7 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm, struct page **pages)
0 : range->flags[HMM_PFN_WRITE];
range->pfn_flags_mask = 0;
range->pfns = pfns;
- hmm_range_register(range, mm, start,
+ hmm_range_register(range, mirror, start,
start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT);

There are also a Kconfig conflict in mm, and an i915 Makefile conflict
that standout.

Feel free to just pull the resolved tree if you want, or get back to
me if this is too messy.

The biggest thing in this apart from the mm/hmm dancing, is the AMD
Navi GPU support, this again contains a bunch of header files that are
large. These are the new AMD RX5700 GPUs that just recently became
available.

Thanks,
Dave.

New drivers:
ST-Ericsson MCDE driver
Ingenic JZ47xx SoC

UAPI change:
HDR source metadata property

Core:
- HDR inforframes and EDID parsing
- drm hdmi infoframe unpacking
- remove prime sg_table caching into dma-buf
- New gem vram helpers to reduce driver code
- Lots of drmP.h removal
- reservation fencing fix
- documentation updates
- drm_fb_helper_connector removed
- mode name command handler rewrite

fbcon:
- Remove the fbcon notifiers

ttm:
- forward progress fixes

dma-buf:
- make mmap call optional
- debugfs refcount fixes
- dma-fence free with pending signals fix
- each dma-buf gets an inode

Panels:
- Lots of additional panel bindings

amdgpu:
- initial navi10 support
- avoid hw reset
- HDR metadata support
- new thermal sensors for vega asics
- RAS fixes
- use HMM rather than MMU notifier
- xgmi topology via kfd
- SR-IOV fixes
- driver reload fixes
- DC use a core bpc attribute
- Aux fixes for DC
- Bandwidth calc updates for DC
- Clock handling refactor
- kfd VEGAM support

vmwgfx:
- Coherent memory support changes

i915:
- HDR Support
- HDMI i2c link
- Icelake multi-segmented gamma support
- GuC firmware update
- Mule Creek Canyon PCH support for EHL
- EHL platform updtes
- move i915.alpha_support to i915.force_probe
- runtime PM refactoring
- VBT parsing refactoring
- DSI fixes
- struct mutex dependency reduction
- GEM code reorg

mali-dp:
- Komeda driver features

msm:
- dsi vs EPROBE_DEFER fixes
- msm8998 snapdragon 835 support
- a540 gpu support
- mdp5 and dpu interconnect support

exynos:
- drmP.h removal

tegra:
- misc fixes

tda998x:
- audio support improvements
- pixel repeated mode support
- quantisation range handling corrections
- HDMI vendor info fix

armada:
- interlace support fix
- overlay/video plane register handling refactor
- add gamma support

rockchip:
- RX3328 support

panfrost:
- expose perf counters via hidden ioctls

vkms:
- enumerate CRC sources list
ast:
- rework BO handling

mgag200:
- rework BO handling

dw-hdmi:
- suspend/resume support

rcar-du:
- R8A774A1 Soc Support
- LVDS dual-link mode support
- Additional formats
- Misc fixes

omapdrm:
- DSI command mode display support

stm
- fb modifier support
- runtime PM support

sun4i:
- use vmap ops

vc4:
- binner bo binding rework

v3d:
- compute shader support
- resync/sync fixes
- job management refactoring

lima:
- NULL pointer in irq handler fix
- scheduler default timeout

virtio:
- fence seqno support
- trace events

bochs:
- misc fixes

tc458767:
- IRQ/HDP handling

sii902x:
- HDMI audio support

atmel-hlcdc:
- misc fixes

meson:
- zpos support

drm-next-2019-07-15-1:
drm main pull request for 5.3-rc1
The following changes since commit 6116b892bd4fd0ddc5f30566a556218bb2e1a9b6:

vga_switcheroo: Depend upon fbcon being built-in, if enabled
(2019-06-26 10:36:49 +0200)

are available in the Git repository at:

git://anongit.freedesktop.org/drm/drm tags/drm-next-2019-07-15-1

for you to fetch changes up to 6dfc43d3a19174faead54575c204aee106225f43:

mm: adjust apply_to_pfn_range interface for dropped token.
(2019-07-15 15:16:20 +1000)

----------------------------------------------------------------
drm main pull request for 5.3-rc1

----------------------------------------------------------------
Abhinav Kumar (2):
drm/msm/dsi: add protection against NULL dsi device
drm/msm/dpu: add icc voting in dpu_mdss_init

Aditya Swarup (1):
drm/i915/icl: Fix setting 10 bit deep color mode

Aidan Wood (2):
drm/amd/display: Properly set DCF clock
drm/amd/display: Properly set u clock

Alex Deucher (37):
drm/amdgpu/vega20: use mode1 reset for RAS and XGMI
drm/amdgpu: use pcie_bandwidth_available rather than open coding it
drm/amdgpu/soc15: skip reset on init
drm/amdgpu: fix a race in GPU reset with IB test (v2)
drm/amdgpu/display: Drop some new CONFIG_DRM_AMD_DC_DCN1_01 guards
Revert "drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu"
drm/amdgpu: return 0 by default in amdgpu_pm_load_smu_firmware
drm/amdgpu: wait to fetch the vbios until after common init
Revert "drm/amd/display: make clk_mgr call enable_pme_wa"
Revert "drm/amd/display: Add Underflow Asserts to dc"
Revert "drm/amd/display: move vmid determination logic out of dc"
Revert "drm/amd/display: Rework CRTC color management"
Revert "drm/amd/display: Use macro for invalid OPP ID"
Revert "drm/amd/display: Copy stream updates onto streams"
drm/amdgpu: add Navi10 pci ids
drm/amd/powerplay/smu11: remove smu_update_table_with_arg
drm/amdgpu/powerplay: add license to smu11 header
drm/amdgpu/powerplay/vega20: use correct table index
drm/amdgpu/gfx10: update to latest golden setting
drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth
drm/amd/display: updates for dcn20_update_bandwidth
drm/amd/display: update dcn2 dc_plane_cap
drm/amdgpu: drop unused df init callback
Merge branch 'drm-next' into drm-next-5.3
drm/amdgpu/powerplay: FEATURE_MASK is 64 bit so use ULL
drm/amdgpu/display: switch udelay to msleep
drm/amdgpu/display: drop ifdefs around comments
drm/amdgpu: fix warning on 32 bit
drm/amdgpu: drop copy/paste leftover to fix big endian
drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
drm/amdgpu/gfx10: use reset default for PA_SC_FIFO_SIZE
drm/amdgpu/display: fix interrupt client id for navi
drm/amdgpu: properly guard DC support in navi code
drm/amdgpu/psp11: simplify the ucode register logic
drm/amdgpu: add missing documentation on new module parameters
drm/amdgpu: properly guard the generic discovery code
drm/amdgpu/navi10: add uclk activity sensor

Amber Lin (1):
drm/amdkfd: Add domain number into gpu_id

Andreas Pretzsch (1):
drm/panel: simple: Add support for EDT ET035012DM6

Andres Rodriguez (2):
drm/edid: parse CEA blocks embedded in DisplayID
drm/edid: use for_each_displayid_db where applicable

Andrew F. Davis (3):
dma-buf: Remove leftover [un]map_atomic comments
dma-buf: Update [un]map documentation to match the other functions
dma-buf: Make mmap callback actually optional

Andrey Grodzovsky (5):
drm/sched: Keep s_fence->parent pointer
drm/scheduler: Add flag to hint the release of guilty job.
drm/amdgpu: Avoid HW reset if guilty job already signaled.
drm/sched: Fix static checker warning for potential NULL ptr
drm/sched: Fix make htmldocs warnings.

Anthony Koo (5):
drm/amd/display: fix multi display seamless boot case
drm/amd/display: do not power on eDP power rail early
drm/amd/display: fix issues with bad AUX reply on some displays
drm/amd/display: fix issue with eDP not detected on driver load
drm/amd/display: do not power on eDP power rail early

Aric Cyr (11):
drm/amd/display: 3.2.28
drm/amd/display: 3.2.29
drm/amd/display: 3.2.30
drm/amd/display: Use VCP for extended colorimetry
drm/amd/display: 3.2.31
drm/amd/display: 3.2.32
drm/amd/display: program manual trigger only for bottom most pipe
drm/amd/display: 3.2.33
drm/amd/display: 3.2.34
drm/amd/display: 3.2.35
drm/amd/display: Intermittent DCN2 pipe hang on mode change

Arnd Bergmann (6):
drm/amdgpu: fix error handling in df_v3_6_pmc_start
drm/komeda: fix 32-bit komeda_crtc_update_clock_ratio
amdgpu: make pmu support optional
drm/amd/display: dcn20: include linux/delay.h
drm/amd/powerplay: vega20: fix uninitialized variable use
drm/amd/display: avoid 64-bit division

Ayan Halder (1):
drm/komeda: Make Komeda interrupts shareable

Benjamin Gaignard (1):
drm/stm: ltdc: restore calls to clk_{enable/disable}

Bhawanpreet Lakha (1):
drm/amd/powerplay: Fix maybe-uninitialized in get_ppfeature_status

Biju Das (4):
dt-bindings: display: renesas: du: Document the r8a774a1 bindings
dt-bindings: display: renesas: lvds: Document r8a774a1 bindings
drm: rcar-du: Add R8A774A1 support
drm: rcar-du: lvds: Add r8a774a1 support

Bob Yang (1):
drm/amd/display: fixed DCC corruption

Boris Brezillon (4):
drm/panfrost: Move gpu_{write, read}() macros to panfrost_regs.h
drm/panfrost: Add a module parameter to expose unstable ioctls
drm/panfrost: Add an helper to check the GPU generation
drm/panfrost: Expose performance counters through unstable ioctls

Brian Masney (2):
drm/msm: correct attempted NULL pointer dereference in put_iova
drm/msm: add dirty framebuffer helper

Charlene Liu (20):
drm/amd/display: add SW_USE_I2C_REG request.
drm/amd/display: color space ycbcr709 support
drm/amd/display: reset retimer/redriver below 340Mhz
drm/amd/display: define v_total_min and max parameters
drm/amd/display: enabling stream after HPD low to high happened
drm/amd/display: add some math functions for dcn_calc_math
drm/amd/display: add audio related regs
drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk.
drm/amd/display: fix can not turn on two displays due to
DSC_RESOURCE failed.
drm/amd/display: Add hubp_init entry to hubp vtable
drm/amd/display: add SW_USE_I2C_REG request.
drm/amd/display: Create DWB resource for DCN2
drm/amd/display: [backport] dwb dm + efc support
drm/amd/display: used optimum VSTARTUP instead of MaxVStartup
drm/amd/display: Return UPDATE_TYPE_FULL on writeback update
drm/amd/display: add some parameters to validate bandwidth functions
drm/amd/display: add dwb stere caps and version
drm/amd/display: add p010 and ayuv plane caps
drm/amd/display: dcn2 use fixed clocks.
drm/amd/display: expose dentist_get_did_from_divider

Chengming Gui (3):
drm/amd/powerplay: Enable "disable dpm" feature to support swSMU
debug (v2)
drm/amd/powerplay: Fix code error for translating int type to
bool type correctly
drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

Chia-I Wu (4):
drm/virtio: set seqno for dma-fence
drm/virtio: trace drm_fence_emit
drm/virtio: add trace events for commands
drm/virtio: allocate fences with GFP_KERNEL

Chris Park (5):
drm/amd/display: Support AVI InfoFrame V3 and V4
drm/amd/display: Define Byte 14 on AVI InfoFrame
drm/amd/display: Move link functions from dc to dc_link
drm/amd/display: Clean up scdc_test_data struct
drm/amd/display: Move link functions from dc to dc_link

Chris Wilson (150):
drm/i915: Verify workarounds immediately after application
drm/i915: Verify the engine workarounds stick on application
drm/i915: Make workaround verification *optional*
drm/i915: Avoid use-after-free in reporting create.size
drm/i915: Stop overwriting RING_IMR in rcs resume
drm/i915: Setup the RCS ring prior to execution
drm/i915: Remove unwarranted clamping for hsw/bdw
drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info
drm/i915: Expose the busyspin durations for i915_wait_request
drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt
drm/i915: Start writeback from the shrinker
dma-buf: Remove unused sync_dump()
drm/i915: Store the default sseu setup on the engine
drm/i915/selftests: Verify whitelist of context registers
drm/i915: Move GraphicsTechnology files under gt/
drm/i915: Introduce struct intel_wakeref
drm/i915: Pull the GEM powermangement coupling into its own file
drm/i915: Introduce context->enter() and context->exit()
drm/i915: Pass intel_context to i915_request_create()
drm/i915: Invert the GEM wakeref hierarchy
drm/i915: Explicitly pin the logical context for execbuf
drm/i915: Allow multiple user handles to the same VM
drm/i915: Disable preemption and sleeping while using the punit sideband
drm/i915: Lift acquiring the vlv punit magic to a common sb-get
drm/i915: Lift sideband locking for vlv_punit_(read|write)
drm/i915: Replace pcu_lock with sb_lock
drm/i915: Separate sideband declarations to intel_sideband.h
drm/i915: Merge sbi read/write into a single accessor
drm/i915: Merge sandybridge_pcode_(read|write)
drm/i915: Move sandybride pcode access to intel_sideband.c
drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
drm/i915: Enable render context support for Ironlake (gen5)
drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)
drm/i915/gvt: Pin the per-engine GVT shadow contexts
drm/i915: Export intel_context_instance()
drm/i915/selftests: Use the real kernel context for sseu isolation tests
drm/i915/selftests: Pass around intel_context for sseu
drm/i915: Pass intel_context to intel_context_pin_lock()
drm/i915: Split engine setup/init into two phases
drm/i915: Switch back to an array of logical per-engine HW contexts
drm/i915: Remove intel_context.active_link
drm/i915: Move i915_request_alloc into selftests/
drm/i915: Skip unused contexts for context_barrier_task()
drm/i915: Wait for the struct_mutex on idling
drm/i915: Move the engine->destroy() vfunc onto the engine
drm/i915: Complete both freed-object passes before draining the workqueue
drm/i915: Include fence signaled bit in print_request()
drm/i915/guc: Fix runtime suspend
drm/i915/execlists: Flush the tasklet on parking
drm/i915: Leave engine parking to the engines
drm/i915/hangcheck: Track context changes
drm/i915: Delay semaphore submission until the start of the signaler
drm/i915: Disable semaphore busywaits on saturated systems
drm/i915: Acquire the signaler's timeline HWSP last
drm/i915: Assert breadcrumbs are correctly ordered in the signal handler
drm/i915: Prefer checking the wakeref itself rather than the counter
drm/i915: Assert the local engine->wakeref is active
drm/i915: Flush the switch-to-kernel-context harder for DROP_IDLE
drm/i915: Remove delay for idle_work
drm/i915: Cancel retire_worker on parking
drm/i915: Stop spinning for DROP_IDLE (debugfs/i915_drop_caches)
drm/i915: Only reschedule the submission tasklet if preemption is possible
drm/i915/execlists: Don't apply priority boost for resets
drm/i915: Reboot CI if forcewake fails
drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD
drm/i915: Seal races between async GPU cancellation, retirement
and signaling
drm/i915: Rearrange i915_scheduler.c
drm/i915: Pass i915_sched_node around internally
drm/i915: Check for no-op priority changes first
drm/i915: Mark semaphores as complete on unsubmit out if payload
was started
drm/i915: Truly bump ready tasks ahead of busywaits
drm/i915/dp: Initialise locals for static analysis
drm/i915/hdcp: Use both bits for device_count
drm/i915: Bump signaler priority on adding a waiter
drm/i915: Downgrade NEWCLIENT to non-preemptive
drm/i915/execlists: Drop promotion on unsubmit
drm/i915: Restore control over ppgtt for context creation ABI
drm/i915: Allow a context to define its set of engines
drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
drm/i915: Re-expose SINGLE_TIMELINE flags for context creation
drm/i915: Allow userspace to clone contexts on creation
drm/i915: Load balancing across a virtual engine
drm/i915: Apply an execution_mask to the virtual_engine
drm/i915: Extend execution fence to support a callback
drm/i915/execlists: Virtual engine bonding
drm/i915: Allow specification of parallel execbuf
drm/i915/gtt: Always acquire struct_mutex for gen6_ppgtt_cleanup
drm/i915/gtt: Neuter the deferred unbind callback from gen6_ppgtt_cleanup
drm/i915: Keep user GGTT alive for a minimum of 250ms
drm/i915: Kill the undead intel_context.c zombie
drm/i915: Split GEM object type definition to its own header
drm/i915: Pull GEM ioctls interface to its own file
drm/i915: Move object->pages API to i915_gem_object.[ch]
drm/i915: Move shmem object setup to its own file
drm/i915: Move phys objects to its own file
drm/i915: Move mmap and friends to its own file
drm/i915: Move GEM domain management to its own file
drm/i915: Move more GEM objects under gem/
drm/i915: Pull scatterlist utils out of i915_gem.h
drm/i915: Move GEM object domain management from struct_mutex to local
drm/i915: Move GEM object waiting to its own file
drm/i915: Move GEM object busy checking to its own file
drm/i915: Move GEM client throttling to its own file
drm/i915: Rename intel_context.active to .inflight
drm/i915: Drop the deferred active reference
drm/i915: Take a runtime pm wakeref for atomic commits
drm/i915: Avoid refcount_inc on known zero count
drm/i915/gtt: Avoid overflowing the WC stash
drm/i915: Drop check for non-NULL entry in llist_for_each_entry_safe
drm/i915: Make default value for i915.mmio_debug a compile time option
drm/i915: Track the purgeable objects on a separate eviction list
drm/i915: Report all objects with allocated pages to the shrinker
drm/i915/selftests: Flush partial-tiling object once
drm/i915: Use unchecked writes for setting up the fences
drm/i915: Use unchecked uncore writes to flush the GTT
drm: Flush output polling on shutdown
drm/i915/gtt: Replace struct_mutex serialisation for allocation
dma-buf: Discard old fence_excl on retrying get_fences_rcu for realloc
drm/i915: Move object close under its own lock
drm/i915: Skip context_barrier emission for unused contexts
drm/i915: Report an earlier wedged event when suspending the engines
dma-fence: Signal all callbacks from dma_fence_release()
drm/i915: Allow interrupts when taking the timeline->mutex
drm/i915: Promote i915->mm.obj_lock to be irqsafe
drm/i915: Pull kref into i915_address_space
drm/i915: Rename i915_hw_ppgtt to i915_ppgtt
drm/i915: Add a label for config DRM_I915_SPIN_REQUEST
drm/i915: Prevent lock-cycles between GPU waits and GPU resets
drm/i915: Combine unbound/bound list tracking for objects
dma-fence/reservation: Markup rcu protected access for DEBUG_MUTEXES
drm/i915: kerneldoc warnings squelched
drm/i915: Move fence register tracking from i915->mm to ggtt
drm/i915: Enable refcount debugging for default debug levels
drm/i915: Discard some redundant cache domain flushes
drm/i915: Execute signal callbacks from no-op i915_request_wait
drm/i915: Refine i915_reset.lock_map
drm/i915: Keep contexts pinned until after the next kernel context switch
drm/i915: Stop retiring along engine
drm/i915: Replace engine->timeline with a plain list
drm/i915: Avoid tainting i915_gem_park() with wakeref.lock
drm/i915/gtt: Serialise both updates to PDE and our shadow
drm/i915/guc: Reduce verbosity on log overflows
drm/i915: Keep engine alive as we retire the context
drm/i915: Use drm_gem_object.resv
drm/i915: Skip shrinking already freed pages
drm/i915/selftests: Flush live_evict
drm/i915: Don't dereference request if it may have been retired
when printing
drm/i915: Make the semaphore saturation mask global
drm/i915/execlists: Detect cross-contamination with GuC
drm/i915: Stop passing I915_WAIT_LOCKED to i915_request_wait()

Christian König (18):
drm/i915: remove DRM_AUTH from IOCTLs which also have DRM_RENDER_ALLOW
drm/scheduler: rework job destruction
MAINTAINERS: drop Jerry as TTM maintainer
dma-buf: start caching of sg_table objects v2
drm: remove prime sg_table caching
drm/amdgpu: rename amdgpu_prime.[ch] into amdgpu_dma_buf.[ch]
drm/amdgpu: remove static GDS, GWS and OA allocation
drm/ttm: Make LRU removal optional v2
drm/ttm: return immediately in case of a signal
drm/ttm: remove manual placement preference
drm/ttm: cleanup ttm_bo_mem_space
drm/ttm: immediately move BOs to the new LRU v3
drm/ttm: fix busy memory to fail other user v10
drm/ttm: fix ttm_bo_unreserve
drm/amdgpu: drop some validation failure messages
drm/amdgpu: create GDS, GWS and OA in system domain
drm/amdgpu: stop removing BOs from the LRU v3
drm/amdgpu: disable concurrent flushes for Navi10 v2

Chunming Zhou (2):
drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpu
drm/amd/display: use ttm_eu_reserve_buffers instead of
amdgpu_bo_reserve v2

Claudiu Beznea (3):
drm: atmel-hlcdc: add config option for clock selection
drm: atmel-hlcdc: avoid initializing cfg with zero
drm/atmel-hlcdc: revert shift by 8

Clinton Taylor (1):
drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

Clément Péron (2):
drm: panfrost: add optional bus_clock
dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible

Colin Ian King (6):
drm/amdgpu: fix spelling mistake "retrived" -> "retrieved"
drm/i915/gtt: set err to -ENOMEM on memory allocation failure
drm/amdkfd: fix null pointer dereference on dev
drm/i915: fix use of uninitialized pointer vaddr
drm/bridge: sii902x: fix comparision of u32 with less than zero
drm/amd/display: fix a couple of spelling mistakes

Dan Carpenter (5):
drm/i915: selftest_lrc: Check the correct variable
drm/bridge: sii902x: re-order conditions to prevent out of bounds read
drm/amdgpu: Fix bounds checking in amdgpu_ras_is_supported()
drm/mcde: Fix an uninitialized variable
drm: self_refresh: Fix a reversed condition in
drm_self_refresh_helper_cleanup()

Daniel Drake (1):
drm/i915/fbc: disable framebuffer compression on GeminiLake

Daniel He (1):
drm/amd/display: Modified AUX_DPHY_RX_CONTROL0

Daniel Vetter (17):
drm/doc: Improve docs for conn_state->best_encoder
drm: Some ocd in drm_file.c
drm/doc: More fine-tuning on userspace review requirements
drm/docs: More links for implicit/explicit fencing.
drm/crc-debugfs: User irqsafe spinlock in drm_crtc_add_crc_entry
drm/vkms: Forward timer right after drm_crtc_handle_vblank
drm/crc-debugfs: Also sprinkle irqrestore over early exits
Merge tag 'du-next-20190608-2' of
git://linuxtv.org/pinchartl/media into drm-next
Merge tag 'omapdrm-5.3' of git://git.kernel.org/.../tomba/linux
into drm-next
drm/fb: document dirty helper better
drm/ast: Drop fb_debug_enter/leave
Merge tag 'drm-misc-next-2019-06-14' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm/todo: Improve drm_gem_object funcs todo
drm/gem: Unexport drm_gem_(un)pin/v(un)map
drm/vkms: Move format arrays to vkms_plane.c
Merge v5.2-rc5 into drm-next
drm/todo: Update drm_gem_object_funcs todo even more

Daniele Ceraolo Spurio (12):
drm/i915: extract intel_display_power.h/c from intel_runtime_pm.h/c
drm/i915: move more defs in intel_display_power.h
drm/i915/guc: always use Command Transport Buffers
drm/i915/wopcm: update default size for gen11+
drm/i915: prefer i915_runtime_pm in intel_runtime function
drm/i915: Remove rpm asserts that use i915
drm/i915: make enable/disable rpm assert function use the rpm structure
drm/i915: move and rename i915_runtime_pm
drm/i915: move a few more functions to accept the rpm structure
drm/i915: update rpm_get/put to use the rpm structure
drm/i915: update with_intel_runtime_pm to use the rpm structure
drm/i915: make intel_wakeref work on the rpm struct

Dave Airlie (20):
Merge tag 'drm-misc-next-2019-05-24' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next
Merge tag 'drm-intel-next-2019-05-24' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next
Merge branch 'drm-next-5.3' of
git://people.freedesktop.org/~agd5f/linux into drm-next
Merge tag 'drm-misc-next-2019-06-05' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next
Merge branch 'drm-next-5.3' of
git://people.freedesktop.org/~agd5f/linux into drm-next
Merge branch 'vmwgfx-next' of
git://people.freedesktop.org/~thomash/linux into drm-next
Merge tag 'drm-misc-next-2019-06-20' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next
Merge tag 'drm-intel-next-2019-06-19' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next
Merge commit 'refs/for-upstream/mali-dp' of
git://linux-arm.org/linux-ld into drm-next
Merge tag 'drm/tegra/for-5.3-rc1' of
git://anongit.freedesktop.org/tegra/linux into drm-next
Merge tag 'for-airlie-tda998x' of
git://git.armlinux.org.uk/~rmk/linux-arm into drm-next
Merge tag 'drm-next-5.3-2019-06-25' of
git://people.freedesktop.org/~agd5f/linux into drm-next
Merge tag 'drm-msm-next-2019-06-25' of
https://gitlab.freedesktop.org/drm/msm into drm-next
Merge tag 'exynos-drm-next-for-v5.3' of
git://git.kernel.org/.../daeinki/drm-exynos into drm-next
Merge tag 'for-airlie-armada' of
git://git.armlinux.org.uk/~rmk/linux-arm into drm-next
Merge tag 'drm-misc-next-fixes-2019-06-27' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next
Merge tag 'drm-next-5.3-2019-06-27' of
git://people.freedesktop.org/~agd5f/linux into drm-next
Merge tag 'drm-next-5.3-2019-07-09' of
git://people.freedesktop.org/~agd5f/linux into drm-next
Merge tag 'imx-drm-next-2019-07-05' of
git://git.pengutronix.de/git/pza/linux into drm-next
mm: adjust apply_to_pfn_range interface for dropped token.

David Riley (4):
drm/virtio: Ensure cached capset entries are valid before copying.
drm/virtio: Wake up all waiters when capset response comes in.
drm/virtio: Fix cache entry creation race.
drm/virtio: Add memory barriers for capset cache.

Deepak Rawat (2):
drm/vmwgfx: Add debug message for layout change ioctl
drm/vmwgfx: Use VMW_DEBUG_KMS for vmwgfx mode-setting user errors

Derek Lai (1):
drm/amd/display: add i2c_hw_Status check to make sure as HW I2c in use

Dmytro Laktyushkin (14):
drm/amd/display: move signal type out of otg dlg params
drm/amd/display: stop external access to internal optc sync params
drm/amd/display: fix acquire_first_split_pipe function
drm/amd/display: add null checks and set update flags
drm/amd/display: move vmid determination logic out of dc
drm/amd/display: clean up validation failure log spam
drm/amd/display: fix dsc validation
drm/amd/display: fix fpga fclk programming
drm/amd/display: fix dcn2 mpc split decision
drm/amd/display: fix odm mpo disable
drm/amd/display: fix macro_tile_size for tiling
drm/amd/display: add null checks and set update flags for DCN2
drm/amd/display: move vmid determination logic to a module
drm/amd/display: add missing mod_vmid destructor

Dongli Zhang (1):
drm/i915: remove unused IO_TLB_SEGPAGES which should be defined by swiotlb

Dongwon Kim (1):
drm/i915/gen11: enable support for headerless msgs

Douglas Anderson (7):
dt-bindings: drm/bridge/synopsys: dw-hdmi: Add "unwedge" for ddc bus
drm/bridge/synopsys: dw-hdmi: Add "unwedge" for ddc bus
drm/bridge/synopsys: dw-hdmi: Fix unwedge crash when no pinctrl entries
drm: bridge: dw-hdmi: Add hook for resume
drm/rockchip: dw_hdmi: Handle suspend/resume
drm/rockchip: Properly adjust to a true clock in adjusted_mode
drm/rockchip: Base adjustments of the mode based on prev adjustments

Emil Velikov (2):
drm/virtio: remove irrelevant DRM_UNLOCKED flag
drm/omap: remove open-coded drm_invalid_op()

Emily Deng (5):
drm/amdgpu: fix unload driver fail
drm/amdgpu: Need to set the baco cap before baco reset
drm/amdgpu:Fix the unpin warning about csb buffer
drm/amdgpu/sriov: Correct some register program method
drm/amdgpu/display: Fix reload driver error

Eric Anholt (11):
drm/v3d: Switch the type of job-> to reduce casting.
drm/v3d: Refactor job management.
drm/v3d: Add support for compute shader dispatch.
drm/v3d: Drop reservation of a shared slot in the dma-buf reservations.
drm/v3d: Add missing implicit synchronization.
drm/doc: Allow new UAPI to be used once it's in drm-next/drm-misc-next.
drm/doc: Document expectation that userspace review looks at kernel uAPI.
drm/v3d: Fix debugfs reads of MMU regs.
drm/v3d: Set the correct DMA mask according to the MMU's limits.
drm/v3d: Dump V3D error debug registers in debugfs, and one at reset.
drm/v3d: Fix and extend MMU error handling.

Eric Bernstein (5):
drm/amd/display: Refactor DIO stream encoder
drm/amd/display: Dont aser if DP_DPHY_INTERNAL_CTRL
drm/amd/display: Refactor DIO stream encoder
drm/amd/display: Alpha plane type
drm/amd/display: expose enable dp output functions

Eric Yang (8):
drm/amd/display: Set dispclk and dprefclock directly
drm/amd/display: move back vbios cmd table for set dprefclk
drm/amd/display: make clk mgr soc specific
drm/amd/display: Move CLK_BASE_INNER macro
drm/amd/display: move clk_mgr files to right place
drm/amd/display: Fix type of pp_smu_wm_set_range struct
drm/amd/display: Refactor clk_mgr functions
drm/amd/display: Refactor clk_mgr functions

Erico Nunes (2):
drm/lima: add timeout to drm scheduler init
drm/scheduler: Fix job cleanup without timeout handler

Ernst Sjöstrand (6):
drm/amd/amdgpu: Indent AMD_IS_APU properly
drm/amd/amdgpu: Fix amdgpu_set_pp_od_clk_voltage error check
drm/amd/amdgpu: amdgpu_hwmon_show_temp: initialize temp
drm/amd/amdgpu: Check stream in amdgpu_dm_commit_planes
drm/amd/amdgpu: Fix style issues in dcn20_resource.c
drm/amd/amdgpu: sdma_v4_0_start: initialize r

Eryk Brol (5):
drm/amd/display: Disable audio stream only if it's currently enabled
drm/amd/display: Ensure DRR triggers in BP
drm/amd/display: Increase Backlight Gain Step Size
drm/amd/display: Ensure DRR triggers in BP
drm/amd/display: Change DCN2 vupdate start programming

Evan Quan (33):
drm/amd/powerplay: support hotspot/memory critical limit values
drm/amd/powerplay: support temperature emergency max values
drm/amd/powerplay: support SMU metrics table on Vega12
drm/amd/powerplay: expose current hotspot and memory temperatures V2
drm/amd/powerplay: support hwmon temperature channel labels V2
drm/amd/powerplay: expose Vega12 current power
drm/amd/powerplay: expose Vega12 current gpu activity
drm/amd/powerplay: expose Vega20 realtime memory utilization
drm/amd/powerplay: expose Vega12 realtime memory utilization
drm/amd/powerplay: expose SMU7 asics realtime memory utilization
drm/amdgpu: add new sysfs interface for memory realtime utilization
drm/amdgpu: enable separate timeout setting for every ring type V4
drm/amd/powerplay: fix Vega10 mclk/socclk voltage link setup
drm/amd/powerplay: valid Vega10 DPMTABLE_OD_UPDATE_VDDC settings V2
drm/amd/powerplay: avoid repeat AVFS enablement/disablement
drm/amd/powerplay: update Vega10 power state on OD
drm/amd/powerplay: force to update all clock tables on OD reset
drm/amd/powerplay: update Vega10 ACG Avfs Gb parameters
drm/amd/powerplay: drop unnecessary sw smu check
drm/amd/powerplay: drop redundant smu call
drm/amd/powerplay: support ppfeatures sysfs interface on sw smu routine
drm/amd/powerplay: honor hw limit on fetching metrics data
drm/amd/powerplay: support uclk activity retrieve on sw smu routine
drm/amd/powerplay: support sw smu hotspot and memory temperature retrieval
drm/amd/powerplay: fix sw SMU wrong UVD/VCE powergate setting
drm/amd/powerplay: enable ppfeaturemask module parameter support on Vega20
drm/amd/powerplay: check gfxclk dpm enablement before proceeding
drm/amd/powerplay: check prerequisite for VCN power gating
drm/amd/powerplay: support runtime ppfeatures setting on Navi10
drm/amd/powerplay: add missing smu_get_clk_info_from_vbios() call
drm/amd/powerplay: no memory activity support on Vega10
drm/amdgpu: fix MGPU fan boost enablement for XGMI reset
drm/amd/powerplay: use hardware fan control if no powerplay fan table

Fabien Dessenne (2):
drm/stm: ltdc: manage the get_irq probe defer case
drm/stm: ltdc: return appropriate error code during probe

Fabio Estevam (4):
dt-bindings: Add vendor prefix for VXT Ltd
dt-bindings: Add VXT VL050-8048NT-C01 panel bindings
drm/panel: simple: Add support for VXT VL050-8048NT-C01 panel
drm/damage-helper: Use NULL instead of 0

Felix Kuehling (10):
drm/amdgpu: Reserve shared fence for eviction fence
drm/amdgpu: Improve error handling for HMM
drm/amdkfd: Fix a circular lock dependency
drm/amdkfd: Simplify eviction state logic
drm/ttm: return -EBUSY if waiting for busy BO fails
drm/amdkfd: Print a warning when the runlist becomes oversubscribed
drm/amdgpu: Use FENCE_OWNER_KFD in process_sync_pds_resv
drm/amdgpu: Fix tracking of invalid userptrs
drm/amdkfd: Add chained_runlist_idle_disable flag to pm4_mes_runlist
drm/amdkfd: Disable idle optimization for chained runlist

Fernando Pacheco (5):
drm/i915/uc: Rename uC firmware init/fini functions
drm/i915/uc: Reserve upper range of GGTT
drm/i915/uc: Place uC firmware in upper range of GGTT
Revert "drm/i915/guc: Disable global reset"
drm/i915/selftests: Check that gpu reset is usable from atomic context

Flora Cui (1):
drm/amdgpu: fix scheduler timeout calc

Fuqian Huang (1):
drm/amdgpu: Use kmemdup rather than duplicating its implementation

Gary Kattan (1):
drm/amd/display: Implement CM dealpha and bias interfaces

Geert Uytterhoeven (2):
drm/i915: Grammar s/the its/its/
drm/amd/display: Add missing newline at end of file

Gen Zhang (1):
drm/edid: Fix a missing-check bug in drm_load_edid_firmware()

Georgi Djakov (1):
drm/msm/mdp5: Use the interconnect API

Gerd Hoffmann (2):
drm/cirrus: remove leftover files
drm/virtio: drop framebuffer dirty tracking code

Greg Hackmann (3):
dma-buf: give each buffer a full-fledged inode
dma-buf: add DMA_BUF_SET_NAME ioctls
dma-buf: add show_fdinfo handler

Greg Kroah-Hartman (17):
vga_switcheroo: no need to check return value of debugfs_create functions
panel: rocktech: no need to check return value of debugfs_create functions
drm: no need to check return value of debugfs_create functions
sti: no need to check return value of debugfs_create functions
host1x: debugfs_create_dir() can never return NULL
radeon: no need to check return value of debugfs_create functions
amdgpu: no need to check return value of debugfs_create functions
amdkfd: no need to check return value of debugfs_create functions
amdgpu_dm: no need to check return value of debugfs_create functions
drm: debugfs: make drm_debugfs_create_files() never fail
drm/vc4: no need to check return value of debugfs_create functions
drm/i915: no need to check return value of debugfs_create functions
msm: adreno: no need to check return value of debugfs_create functions
msm: dpu1: no need to check return value of debugfs_create functions
msm: no need to check return value of debugfs_create functions
komeda: no need to check return value of debugfs_create functions
malidp: no need to check return value of debugfs_create functions

Gurchetan Singh (1):
drm/virtio: use u64_to_user_ptr macro

Gwan-gyeong Mun (6):
drm/i915/dp: Add a config function for YCBCR420 outputs
drm: Rename struct edp_vsc_psr to struct dp_sdp
drm/i915/dp: Program VSC Header and DB for Pixel
Encoding/Colorimetry Format
drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
drm/i915/dp: Change a link bandwidth computation for DP
drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

Hans de Goede (7):
drm/i915/dsi: Call drm_connector_cleanup on vlv_dsi_init error exit path
drm/i915/dsi: Use a fuzzy check for burst mode clock check
drm: panel-orientation-quirks: Add quirk for GPD pocket2
drm: panel-orientation-quirks: Add quirk for GPD MicroPC
drm/i915/dsi: Move logging of DSI VBT parameters to a helper function
drm/i915/dsi: Move vlv/icl_dphy_param_init call out of
intel_dsi_vbt_init (v2)
drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)

Hariprasad Kelam (2):
drm/bridge: analogix_dp: possible condition with no effect (if == else)
drm/amd/display: fix compilation error

Harish Kasiviswanathan (1):
drm/amdkfd: Fix compute profile switching

Harmanprit Tatla (1):
drm/amd/display: Gamma logic limitations causing unintended use
of RAM over ROM.

Harry Wentland (26):
drm/amd/display: Add ASICREV_IS_PICASSO
drm/amd/display: Don't load DMCU for Raven 1 (v2)
drm/amd/display: Drop DCN1_01 guards
drm/amd/display: Read soc_bounding_box from gpu_info (v2)
drm/amd/display: Add DCN2 and NV ASIC ID
drm/amd/display: add AUX and I2C for DCN2
drm/amd/display: Add GPIO support for DCN2
drm/amd/display: Add DCN2 BIOS parsing
drm/amd/display: Add DCN2 IRQ handling
drm/amd/display: Add DCN2 changes to DML
drm/amd/display: Add DCN2 DIO
drm/amd/display: Add DCN2 clk mgr
drm/amd/display: Add DCN2 OPTC
drm/amd/display: Add DCN2 OPP
drm/amd/display: Add DCN2 MPC
drm/amd/display: Add DCN2 DPP
drm/amd/display: Add DCN2 HUBP and HUBBUB
drm/amd/display: Add DCN2 MMHUBBUB
drm/amd/display: Add DCN2 DWB
drm/amd/display: Add DCN2 IPP
drm/amd/display: Add DCN2 VMID
drm/amd/display: Add DCN2 HW Sequencer and Resource
drm/amd/display: Add DC core changes for DCN2
drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
drm/amdgpu: Enable DC support for Navi10
drm/amd/display: Add DSC support for Navi (v2)

Hawking Zhang (83):
drm/amdgpu/psp: udpate ta_ras interface header
drm/amdgpu: add ATHUB 2.0 register headers
drm/amdgpu: add CLK 11.0 register headers
drm/amdgpu: add DCN 2.0 register headers
drm/amdgpu: add HDP 5.0 register headers
drm/amdgpu: add MP 11.0 register headers
drm/amdgpu: add NBIO 2.3 register headers
drm/amdgpu: add VCN 2.0 register headers
drm/amdgpu: add GC 10.1 register headers (v4)
drm/amdgpu: add MMHUB 2.0 register headers
drm/amdgpu: add OSS 5.0 register headers
drm/amdgpu: add SMUIO 11.0 register headers
drm/amdgpu: add navi10 enums header
drm/amdgpu: atomfirmware.h updates for navi10
drm/amdgpu: add doorbell assignement for navi10
drm/amdgpu: add navi10 ip offset header
drm/amdgpu: Add GDDR6 in vram_name arrary
drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config
drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override
drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10
drm/amdgpu: parse the new members added by gpu_info ucode v1_1
drm/amdgpu: add sdma v5 packet header file
drm/amdgpu: add navi pm4 header
drm/amdgpu: query vram type from atomfirmware vram_info
drm/amdgpu: query vram_width from vram_info table
drm/amdgpu: add nbio v2.3 for navi10 (v4)
drm/amdgpu/gfx10: new approach to load pfp fw (v4)
drm/amdgpu/gfx10: new approach to load ce fw (v4)
drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4)
drm/amdgpu: add members in amdgpu_me for gfx queue
drm/amdgpu: acquire available gfx queues
drm/amdgpu: add helper function for gfx queue/bitmap transition
drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init
drm/amdgpu: Move common code to amdgpu_gfx.c
drm/amdgpu: enable gfx eop interrupt per gfx pipe
drm/amdgpu: add module parameter for async_gfx_ring enablement
drm/amdgpu: create mqd for gfx queues on navi10
drm/amdgpu: add new HDP CG flags
drm/amdgpu: add flag to support IH clock gating
drm/amdgpu: correct pte mtype field for navi
drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10
drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)
drm/amdgpu: add mmhub v2 block for navi10 (v4)
drm/amdgpu: add gmc v10 ip block for navi10 (v6)
drm/amdgpu: add irq sources for gfx v10_1
drm/amdgpu: add irq sources for sdma v5_0
drm/amdgpu: add irq sources for vcn v2_0 (v2)
drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/
drm/amdgpu: add navi10 ih ip block (v3)
drm/amdgpu: add structure to support build-in toc to psp sos
drm/amdgpu/psp: support init psp sos microcode with build-in toc
drm/amdgpu: use rlc toc from psp sos binary
drm/amdgpu: rename rlc autoload to backdoor autoload
drm/amdgpu: add helper function to print psp hdr
drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode
drm/amdgpu/psp: support print out psp firmware header v1_1 info
drm/amdgpu/psp: add structure to support load toc in psp (v2)
drm/amdgpu/psp: add support to load TOC to psp
drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware
drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size
drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sos
drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2)
drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_init
drm/amd/amdgpu: add flag to mark whether autoload is supported or not
drm/amdgpu/psp: skip mec jt when autoload is enabled
drm/amdgpu: enable psp front door loading by default on navi10
drm/amdgpu: declare navi10 asd firmware
drm/amdgpu/psp11: skip ta firmware for navi10
drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_device
drm/amdgpu: set the default value of pa_sc_tile_steering_override
drm/amdgpu: add initial support for sdma v5.0 (v6)
drm/amdgpu: add gfx v10 implementation (v10)
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10
drm/amdgpu: add navi10 common ip block (v3)
drm/amdgpu: Add navi10 kfd support for amdgpu (v3)
drm/amdgpu: update golden setting programming logic
drm/amdgpu: enable sw smu driver for navi10 by default
drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)
drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
drm/amd/powerplay: fix no statements in function returning non-void
drm/amdgpu: initialize THM & CLK IP registers base address
drm/amd/display: enable DSC support by default
drm/amdgpu: fix modprobe failure for uvd_4/5/6

Huang Rui (40):
drm/amdgpu: add navi10 asic type
drm/amdgpu: add NV series gpu family id
drm/amdgpu: add GDDR6 vram type
drm/amdgpu: add navi10 gpu info firmware
drm/amdgpu: add v10 structs header (v2)
drm/amdgpu: add gfx v10 clear state header v2
drm/amdgpu: set navi10's fw loading type as direct
drm/amdgpu: load smc ucode at first with psp while rlc auto load
is supported
drm/amdgpu: add to set navi ip blocks
drm/amd/powerplay: update smu v11 ppsmc header
drm/amd/powerplay: update smu 11 driver if header for navi10
drm/amd/powerplay: fix the mp/smuio header for navi10
drm/amd/powerplay: introduce the navi10 pptable implementation
drm/amd/powerplay: set smu v11 funcs for navi10
drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt
functions setting
drm/amd/powerplay: move bootup value before read pptable from vbios
drm/amd/powerplay: update smu11 driver if header for navi10 (v2)
drm/amdgpu: bump smc firmware header version to v2 (v2)
drm/amdgpu: fix the issue of checking on message mapping
drm/amd/powerplay: smu needs to be initialized after rlc in direct mode
drm/amd/powerplay: introduce the function to load the soft
pptable for navi10 (v2)
drm/amd/powerplay: modify the feature mask to enable gfx/soc dpm
drm/amd/powerplay: skip od feature on navi10 for the moment
drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic
drm/amd/powerplay: introduce smu feature type to handle feature
mask for each asic
drm/amd/powerplay: introduce smu table id type to handle the smu
table for each asic
drm/amd/powerplay: init table_count for smu tables on asic level
drm/amd/powerplay: add tables_init interface for each asic
drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx
as the input
drm/amd/powerplay: use the table size member in the structure
instead of getting directly
drm/amd/powerplay: move PPTable_t uses into asic level
drm/amd/powerplay: move SmuMetrics_t uses into asic level
drm/amd/powerplay: move Watermarks_t uses into asic level
drm/amd/powerplay: introduce smu power source type to handle
AC/DC source for each asic
drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level
drm/amd/powerplay: don't include the smu11 driver if header in
smu v11 (v2)
drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN
DPM is workable
drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm
drm/amd/powerplay: make mmhub pg bit configured by pg_flags
drm/amd/powerplay: make athub pg bit configured by pg_flags

Hugo Hu (1):
drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1D

Icenowy Zheng (1):
dt-bindings: gpu: add bus clock for Mali Midgard GPUs

Ilya Bakoulin (8):
drm/amd/display: Add writeback_config to VBA vars
drm/amd/display: Add writeback_config to VBA vars
drm/amd/display: Fix DCFCLK and SOCCLK not set
drm/amd/display: Fix ODM combine data format
drm/amd/display: Fix LB BPP and Cursor width
drm/amd/display: Drive-by fixes for display_mode_vba
drm/amd/display: Fix incorrect DML output_bpp value
drm/amd/display: Fix incorrect vba type

Imre Deak (19):
drm/i915/icl: Fix MG_DP_MODE() register programming
drm/i915/icl: Factor out combo PHY lane power setup helper
drm/i915/icl: Add missing combo PHY lane power setup
drm/i915: Tune down WARN about incorrect VBT TC legacy flag
drm/i915/icl: More workaround for port F detection due to broken VBTs
drm/i915: Add support for tracking wakerefs w/o power-on guarantee
drm/i915: Force printing wakeref tacking during pm_cleanup
drm/i915: Verify power domains state during suspend in all cases
drm/i915: Add support for asynchronous display power disabling
drm/i915: Disable power asynchronously during DP AUX transfers
drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
drm/i915: Assert that TypeC ports are not used for eDP
drm/i915/icl: Fix AUX-B HW not done issue w/o AUX-A
drm/mst: Fix MST sideband up-reply failure handling
drm/i915/icl: Ensure port A combo PHY HW state is correct

Jack Xiao (51):
drm/amdgpu/gfx10: add special unmap_queues packet for preemption
drm/amdgpu: enable async gfx ring by default
drm/amdgpu/athub2: enable athub2 clock gating
drm/amdgpu: refine the PTE encoding of PRT for navi10
drm/amdgpu: add the trailing fence per ring
drm/amdgpu: add mcbp driver parameter
drm/amdgpu: enable the static csa when mcbp enabled
drm/amdgpu: add ib preemption status in amdgpu_job (v2)
drm/amdgpu/sdma: allocate CSA per sdma ring
drm/amdgpu: program for resuming preempted ib
drm/amdgpu: add mcbp unit test in debugfs (v3)
drm/amdgpu: mark the partial job as preempted in mcbp unit test
drm/amdgpu/mes: add amdgpu_mes driver parameter
drm/amdgpu/mes: add mes header file and definition
drm/amdgpu/mes: add definitions of ip callback function
drm/amdgpu/mes: enable mes on navi10 and later asic
drm/amdgpu/mes10.1: add ip block mes10.1 (v2)
drm/amdgpu/gfx10: fix issues for suspend/resume
drm/amdgpu/vcn2: notify SMU power up/down VCN
drm/amdgpu/vcn2: don't access register when power gated
drm/amdgpu: enable vcn dpm scheme for navi
drm/amdgpu/nv: set vcn pg flag
drm/amdgpu/sdma5: incorrect variable type for gpu address
drm/amdgpu/ucode: add the definitions of MES ucode and ucode data
drm/amdgpu/ucode: add mes firmware file support
drm/amdgpu/mes10.1: add mes firmware info fields
drm/amdgpu/mes10.1: load mes firmware file to CPU buffer
drm/amdgpu/mes10.1: implement ucode CPU buffer destruction
drm/amdgpu/mes10.1: upload mes ucode to gpu buffer
drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer
drm/amdgpu/mes10.1: implement ucode buffers destruction
drm/amdgpu/mes10.1: implement MES firmware backdoor loading
drm/amdgpu/mes10.1: implement mes enablement function
drm/amdgpu/mes10.1: enable mes FW backdoor loading
drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled
drm/amdgpu: RLC must be disabled after SMU when S3 on navi
drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactive
drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resume
drm/amd: the data retured from PRT is expected to be 0
drm/amdgpu/psp: add new VCN RAM ucode id to psp
drm/amdgpu: add corresponding vcn ram ucode id
drm/amdgpu/psp: convert ucode id to psp ucode id
drm/amdgpu/psp: add new psp interface for vcn updating sram
drm/amd/powerplay: update smu11_driver_if_navi10.h
drm/amd/powerplay: disable fw dstate when gfxoff is enabled
drm/amd/powerplay: enable BACO feature as WAR
drm/amdgpu: add field indicating if has PCIE atomics support
drm/amdgpu: enable PCIE atomics ops support
drm/amdkfd: remove duplicated PCIE atomics request
drm/amdkfd: remove an unused variable
drm/amd/powerplay: increase waiting time for smu response

Jack Zhang (1):
drm/amdgpu/sriov: fix Tonga load driver failed

Jagadeesh Pagadala (1):
gpu/drm: Remove duplicate headers

Jagan Teki (4):
dt-bindings: display: Document FriendlyELEC HD702E LCD panel
drm/panel: simple: Add FriendlyELEC HD702E 800x1280 LCD panel
drm/sun4i: sun6i_mipi_dsi: Support DSI GENERIC_SHORT_WRITE_2 transfer
drm/panel: st7701: Swap vertical front and back porch timings

James Clarke (1):
drm: Fix drm.h uapi header for GNU/kFreeBSD

James Zhu (6):
drm/amdgpu: add EDC counter register
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
drm/amdgpu: Fix S3 test issue
drm/amdgpu: Fixed missing to clear some EDC count
drm/amdgpu: Add GDS clearing workaround in later init for gfx9
drm/amdgpu: explicitly set mmGDS_VMID0_BASE to 0

Jani Nikula (69):
Merge drm/drm-next into drm-intel-next-queued
drm/i915: ensure more headers remain self-contained
drm/i915: make intel_bios.h self-contained
drm/i915/dvo: rename dvo.h to intel_dvo_dev.h and make self-contained
drm/i915: make intel_dpll_mgr.h self-contained
drm/i915: move dsi init functions to intel_dsi.h
drm/i915: extract intel_fifo_underrun.h from intel_drv.h
drm/i915: extract intel_dp_link_training.h from intel_drv.h
drm/i915: extract intel_dp_aux_backlight.h from intel_drv.h
drm/i915: extract i915_irq.h from intel_drv.h and i915_drv.h
drm/i915: extract intel_hotplug.h from intel_drv.h and i915_drv.h
drm/i915: extract intel_bios.h functions from i915_drv.h
drm/i915: extract intel_quirks.h from intel_drv.h
drm/i915: extract intel_overlay.h from intel_drv.h and i915_drv.h
drm/i915: extract intel_vdsc.h from intel_drv.h and i915_drv.h
drm/i915: extract intel_dp_mst.h from intel_drv.h
drm/i915: extract intel_dsi_dcs_backlight.h from intel_drv.h
drm/i915: extract intel_atomic.h from intel_drv.h
drm/i915: extract intel_runtime_pm.h from intel_drv.h
drm/i915: move some leftovers to intel_pm.h from i915_drv.h
drm/i915: extract intel_combo_phy.h from i915_drv.h
drm/i915/csr: alpha_support doesn't depend on csr or vice versa
drm/i915: add single combo phy init/unit functions
drm/i915/dvo: move DVO chip types to intel_dvo.c
drm/i915/dsi: move operation mode types to intel_dsi.h
drm/i915: move ranges to intel_display.c
drm/i915: remove unused/stale macros and comments from intel_drv.h
drm/i915/csr: move CSR version macros to intel_csr.h
drm/i915: extract intel_dpio_phy.h from i915_drv.h
drm/i915: extract intel_lpe_audio.h from i915_drv.h
drm/i915: extract intel_acpi.h from i915_drv.h
drm/i915: extract i915_debugfs.h from i915_drv.h
drm/i915: move i915_vgacntrl_reg() where needed
drm/i915: make i915_utils.h self-contained
drm/i915: move more generic utils to i915_utils.h
drm/i915: extract intel_gmbus.h from i915_drv.h and rename intel_i2c.c
drm/dp: drmP.h include removal
drm/edid: drmP.h include removal
drm/i915: Update DRIVER_DATE to 20190523
drm/i915: remove duplicate typedef for intel_wakeref_t
drm/i915: Update DRIVER_DATE to 20190524
drm/i915: make REG_BIT() and REG_GENMASK() work with variables
Merge drm/drm-next into drm-intel-next-queued
Revert "drm/i915: Expand subslice mask"
drm/i915: add force_probe module parameter to replace alpha_support
drm/i915/bios: make child device order the priority order
drm/i915/bios: store child device pointer in DDI port info
drm/i915/bios: refactor DDC pin and AUX CH sanitize functions
drm/i915/bios: use port info child pointer to determine HPD invert
drm/i915/bios: use port info child pointer to determine LSPCON presence
drm/i915/bios: clean up VBT port info debug logging
drm/i915/bios: remove unused, obsolete VBT definitions
drm/i915/bios: reserve struct bdb_ prefix for BDB blocks
drm/i915/bios: add BDB block comments before definitions
drm/i915/bios: sort BDB block definitions using block ID
drm/i915/bios: add VBT swing bit to child device definition
drm/i915/bios: add more LFP options
drm/i915/bios: add an enum for BDB block IDs
Documentation/i915: Fix kernel-doc references to moved gem files
drm/i915: fix documentation build warnings
drm/i915: move pm related declarations to intel_pm.h
drm/i915: remove some unused declarations from intel_drv.h
drm/i915: move more atomic plane declarations to intel_atomic_plane.h
drm/i915/frontbuffer: remove obsolete comment about mark busy/idle
drm/i915: make intel_sdvo_regs.h self-contained
drm/i915: move modesetting output/encoder code under display/
drm/i915: move modesetting core code under display/
Documentation/i915: fix file references after display/ subdir renames
drm/i915: Update DRIVER_DATE to 20190619

Janusz Krzysztofik (2):
drm/i915: Use drm_dev_unplug()
drm/i915: Split off pci_driver.remove() tail to drm_driver.release()

Jay Cornwall (5):
drm/amdkfd: Fix gfx8 MEM_VIOL exception handler
drm/amdkfd: Preserve wave state after instruction fetch MEM_VIOL
drm/amdkfd: Fix gfx9 XNACK state save/restore
drm/amdkfd: Preserve ttmp[4:5] instead of ttmp[14:15]
drm/amdkfd: Implement queue priority controls for gfx9

Jayant Shekhar (3):
drm/msm/dpu: clean up references of DPU custom bus scaling
drm/msm/dpu: Integrate interconnect API in MDSS
dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845

Jeffrey Hugo (6):
drm/msm/mdp5: Fix mdp5_cfg_init error return
dt-bindings: msm/dsi: Add 10nm phy for msm8998 compatible
drm/msm/dsi: Add support for MSM8998 10nm dsi phy
drm/msm/dsi: Add old timings quirk for 10nm phy
drm/msm/dsi: Add support for MSM8998 DSI controller
drm/msm/adreno: Add A540 support

Jerome Brunet (1):
drm/meson: imply dw-hdmi i2s audio for meson hdmi

John Harrison (3):
drm/i915: Support flags in whitlist WAs
drm/i915: Support whitelist workarounds on all engines
drm/i915: Add whitelist workarounds for ICL

Jonas Karlman (1):
drm: Add reference counting on HDR metadata blob

Jonathan Bakker (1):
dt-bindings: panel: Add Samsung S6E63M0 panel documentation

Jonathan Kim (4):
drm/amdgpu: add df perfmon regs and funcs for xgmi
drm/amdgpu: update df_v3_6 for xgmi perfmons (v2)
drm/amdgpu: add pmu counters
drm/amdgpu: add sw_init to df_v1_7

Jordan Crouse (7):
drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets
drm/msm: Print all 64 bits of the faulting IOMMU address
drm/msm: Pass the MMU domain index in struct msm_file_private
drm/msm/dpu: Fix error recovery after failing to enable clocks
drm/msm/dpu: Avoid a null de-ref while recovering from kms init fail
drm/msm/adreno: Call pm_runtime_force_suspend() during unbind
drm/msm/adreno: Ensure that the zap shader region is big enough

Jordan Lazare (1):
drm/amd/display: Remove superflous error message

Joshua Aberback (8):
drm/amd/display: Program VTG params after programming Global Sync
drm/amd/display: Rename EDID_BLOCK_SIZE to DC_EDID_BLOCK_SIZE
drm/amd/display: Program VTG params after programming Global Sync for DCN2
drm/amd/display: Remove dependency on pipe->plane for immedaite
flip status
drm/amd/display: Optimize bandwidth validation by adding early return
drm/amd/display: Add profiling tools for bandwidth validation
drm/amd/display: Remove OPP clock programming on plane disable
drm/amd/display: Set test pattern on blank when using Visual Confirm

Josip Pavic (1):
drm/amd/display: enable abm on dcn2

José Roberto de Souza (1):
drm/i915/psr: Force manual PSR exit in older gens

Jun Lei (10):
drm/amd/display: add support for disconnected eDP panels
drm/amd/display: dont set otg offset
drm/amd/display: Add min_dcfclk_mhz field to bb overrides
drm/amd/display: update calculated bounding box logic for NV
drm/amd/display: fix pstate allow handling in dcn2
drm/amd/display: always use 4 dp lanes for dml
drm/amd/display: Add missing VM conversion from hw values
drm/amd/display: add support for forcing DCFCLK without
affecting watermarks
drm/amd/display: making DCN20 WM table non-overlapping
drm/amd/display: update DCN2 uclk switch time

Justin Swartz (1):
drm/rockchip: dw_hdmi: add basic rk3228 support

Jyri Sarha (7):
dt-bindings: drm/panel: simple: Add binding for TFC S9700RTWV43TR-01B
drm/panel: simple: Add TFC S9700RTWV43TR-01B 800x480 panel support
drm/bridge: sii902x: Set output mode to HDMI or DVI according to EDID
drm/bridge: sii902x: pixel clock unit is 10kHz instead of 1kHz
dt-bindings: display: sii902x: Remove trailing white space
dt-bindings: display: sii902x: Add HDMI audio bindings
drm/bridge: sii902x: Implement HDMI audio support

Jérôme Glisse (1):
dma-buf: balance refcount inbalance

Kefeng Wang (1):
drm/omap: Use dev_get_drvdata()

Kenneth Feng (15):
drm/amd/powerplay: enable backdoor smu fw loading (v2)
drm/amd/powerplay: enable power features
drm/amd: add gfxoff support on navi10
drm/amd/amdgpu: fw version check with gfxoff
drm/amd/powerplay: gfxoff-seperate the Vega20 case
drm/amd/powerplay: enable DCEFCLK dpm support
drm/amd/powerplay: fix the incorrect type of pptable
drm/amd/powerplay: update smu11_driver_if_navi10.h
drm/amd/powerplay: enable vcn powergating v2
drm/amd/powerplay: add new interface for vcn powergating
amd/powerplay: fix the issue of uclk dpm
amd/powerplay: enable uclk dpm
amd/powerplay: update the vcn pg
drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10
drm/amd/powerplay: enable ac/dc feature on navi10

Kent Russell (8):
drm/amdgpu: Add replay counter defines to NBIO headers
drm/amdgpu: Add PCIe replay count sysfs file
drm/amdgpu: Fix CIK references in gmc_v8
drm/amdkfd: Cosmetic cleanup
drm/amdkfd: Add VegaM support
drm/amdgpu: Add Unique Identifier sysfs file unique_id v2
drm/amdgpu: Add CHIP_VEGAM to amdgpu_amdkfd_device_probe
drm/amdkfd: Add procfs-style information for KFD processes

Kevin Wang (62):
drm/amd/powerplay: add helper function to get smu firmware & if version
drm/amd/powerplay: move the funciton of conv_profile_to_workload
to asic file
drm/amd/powerplay: move the function of get[set]_power_profile
to asic file
drm/amd/powerplay: move the function of uvd&vce dpm to asic file
drm/amd/powerplay: move the function of read_sensor to asic file
drm/amd/powerplay: move the function of is_dpm_running to asic file
drm/amd/powerplay: add smu11 smu_if_version check for navi10
drm/amd/powerplay: implement smc firmware v2.1 for smu11
drm/amd/powerplay: remove duplicate code from smu hw init
drm/amd/powerplay: optimization feature mask function for asic
drm/amd/powerplay: add allowed feature mask for navi10
drm/amd/powerplay: add function get current clock freq interface
for navi10
drm/amd/powerplay: add helper function to get dpm freq informations
drm/amd/powerplay: add function print_clk_levels for navi10
drm/amd/powerplay: add helper function of smu_get_dpm_freq_range
drm/amd/powerplay: add helper function of smu_set_soft_freq_range
drm/amd/powerplay: add helper function of smu_set_hard_freq_range
drm/amd/powerplay: add function force_clk_levels for navi10
drm/amd/powerplay: add function populate_umd_state_clk for navi10
drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10
drm/amd/powerplay: add function pre_display_config_changed for navi10
drm/amd/powerplay: add function display_configuration_changed for navi10
drm/amd/powerplay: add funciton force_dpm_limit for navi10
drm/amd/powerplay: add function unforce_dpm_levels for navi10
drm/amd/powerplay: add function get_gpu_power for navi10
drm/amd/powerplay: add function get_current_activity_percent for navi10
drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu file
drm/amd/powerplay: add function is_dpm_running for navi10
drm/amd/powerplay: add function set_thermal_fan_table for navi10
drm/amd/powerplay: add function get_fan_speed_percent for navi10
drm/amd/powerplay: remove upload_dpm_level function for vega20
drm/amd/powerplay: add function get_workload_type_map for swsmu
drm/amd/powerplay: add funciton get[set]_power_profile_mode for
navi10 (v2)
drm/amd/powerplay: add function get_profiling_clk_mask for navi10
drm/amd/powerplay: add function notify_smc_display_config_change
for navi10
drm/amd/powerplay: add function set_watermarks_table function for navi10
drm/amd/powerplay: add function read_sensor for navi10
drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)
drm/amd/powerplay: simplify the interface of get_current_activity_percent
drm/amd/powerplay: simplify the interface of get_gpu_power
drm/amd/powerplay: fix amdgpu_pm_info show gpu load error
drm/amd/powerplay: add sclk sysfs interface support for navi10
drm/amd/powerplay: enable uclk dpm default on navi10
drm/amd/powerplay: move power_dpm_force_performance_level to
amdgpu_smu file
drm/amd/powerplay: move function get_metrics_table to vega20_ppt
drm/amd/powerplay: move function thermal_get_temperature to veag20_ppt
drm/amd/powerplay: add thermal ctf support for navi10
drm/amd/powerplay: remove smu mutex lock in smu_hw_init
drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)
drm/amd/powerplay: fix deadlock issue for smu_force_performance_level
drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK
drm/amd/powerplay: move od8_setting helper function to vega20_ppt
drm/amd/powerplay: move od_default_setting callback to asic file
drm/amd/powerplay: simplified od_settings for each asic
drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled
drm/amd/powerplay: remove unsupport function
set_thermal_fan_table for navi10
drm/amd/powerplay: fix fan speed show error (for hwmon pwm)
drm/amd/powerplay: print smu versions only if version mismatch
drm/amd/powerplay: add feature check in unforce_dpm_levels function (v2)
drm/amd/powerplay: add baco smu reset function for smu11
drm/amdgpu: add mode1 (psp) reset for navi asic
drm/amd/powerplay: add temperature sensor support for navi10

Kieran Bingham (1):
drm: rcar-du: writeback: include interface header

Krunoslav Kovac (3):
drm/amd/display: Add GSL source select registers
drm/amd/display: CS_TFM_1D only applied post EOTF
drm/amd/display: fix gamma logic breaking driver unload

Laurent Pinchart (11):
drm: bridge: Add dual_link field to the drm_bridge_timings structure
dt-bindings: display: bridge: thc63lvd1024: Document dual-link operation
drm: bridge: thc63: Report input bus mode through bridge timings
dt-bindings: display: renesas: lvds: Add renesas,companion property
drm: rcar-du: lvds: Remove LVDS double-enable checks
drm: rcar-du: lvds: Add support for dual-link mode
drm: rcar-du: Skip LVDS1 output on Gen3 when using dual-link LVDS mode
drm: rcar-du: Add support for missing 32-bit RGB formats
drm: rcar-du: Add support for missing 16-bit RGB4444 formats
drm: rcar-du: Add support for missing 16-bit RGB1555 formats
drm: Add drm_atomic_get_(old|new)_connector_for_encoder() helpers

Le.Ma (3):
drm/amdgpu: add structures for buffer allocate/release for rlc autoload
drm/amdgpu: add fw load type flag for rlc autoload
drm/amdgpu: enable virtual display feature for navi10

Leo (Hanghong) Ma (2):
drm/amd/display: Expose send immediate sdp message interface
drm/amd/display: Expose send immediate sdp message interface

Leo Li (5):
drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h
drm/amd/display: Disconnect DCN2 mpcc when changing tg
drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()
drm/amd/display: Guard DML_FAIL_DSC_VALIDATION_FAILURE
drm/amd/display: Properly guard display_mode_vba with DCN2

Leo Liu (23):
drm/amdgpu: add no_user_fence flag to ring funcs
drm/amdgpu/UVD: set no_user_fence flag to true
drm/amdgpu/VCE: set no_user_fence flag to true
drm/amdgpu/VCN: set no_user_fence flag to true
drm/amdgpu: check no_user_fence flag for engines
drm/amdgpu: move the VCN DPG mode read and write to VCN
drm/amdgpu: make VCN DPG pause mode detached from general VCN
drm/amdgpu: add nbio callbacks for vcn doorbell support
drm/amdgpu: add Navi10 VCN firmware support
drm/amdgpu: add VCN2.0 decode ring test
drm/amdgpu: add VCN2.0 decode ib test
drm/amdgpu: add JPEG2.0 decode ring test
drm/amdgpu: add JPEG2.0 decode ring ib test
drm/amdgpu: add initial VCN2.0 support (v2)
drm/amdgpu/VCN2.0: remove powergating for UVDW tile
drm/amdgpu/VCN2.0 remove unused Macro and declaration
drm/amdgpu/VCN2.0: add direct SRAM read and write
drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
drm/amdgpu/VCN2.0: add DPG pause mode
drm/amdgpu: enable VCN2.0 DPG mode
drm/amdgpu/VCN: add buffer for indirect SRAM usage
drm/amdgpu/VCN: implement indirect DPG SRAM mode
drm/amdgpu/VCN: enable indirect DPG SRAM mode

Linus Walleij (4):
drm/atomic-helper: Bump vblank timeout to 100 ms
drm/mcde: Add new driver for ST-Ericsson MCDE
drm/bridge: analogix-anx78xx: Drop of_gpio.h include
drm/bridge: analogix_dp: Convert to GPIO descriptors

Lionel Landwerlin (1):
drm/i915/perf: fix whitelist on Gen10+

Liviu Dudau (1):
arm/komeda: Convert dp_wait_cond() to return an error code.

Louis Li (1):
drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2)

Lowry Li (Arm Technology China) (10):
drm/komeda: Creates plane alpha and blend mode properties
drm/komeda: Clear enable bit in CU_INPUTx_CONTROL
drm/komeda: Add rotation support on Komeda driver
drm/komeda: Adds limitation check for AFBC wide block not support Rot90
drm/komeda: Update HW up-sampling on D71
drm/komeda: Enable color-encoding (YUV format) support
drm/komeda: Adds SMMU support
dt/bindings: drm/komeda: Adds SMMU support for D71 devicetree
drm/komeda: Adds zorder support
drm/komeda: Add slave pipeline support

Lubomir Rintel (1):
drm/armada: replace the simple-framebuffer

Lucas De Marchi (16):
drm/i915/icl: fix step numbers in icl_display_core_init()
drm/i915: reorder if chain to have last gen first
drm/i915: do not mix workaround with normal flow
drm/i915/dmc: protect against reading random memory
drm/i915/icl: use ranges for voltage level lookup
drm/i915/cnl: use ranges for voltage level lookup
drm/i915/skl: use ranges for voltage level lookup
drm/i915/dmc: use kernel types
drm/i915/dmc: extract fw_info and table walk from intel_package_header
drm/i915/dmc: add support for package_header with version 2
drm/i915/dmc: extract function to parse css header
drm/i915/dmc: extract function to parse package_header
drm/i915/dmc: extract function to parse dmc_header
drm/i915/dmc: add support to load dmc_header version 3
drm/i915/dmc: remove redundant return in parse_csr_fw()
drm/i915/dmc: protect against loading wrong firmware

Lukasz Majewski (2):
dt-bindings: display/panel: Add KOE tx14d24vm1bpa display description
drm/panel: simple: Add KOE tx14d24vm1bpa display support (320x240)

Lyude Paul (1):
drm/amdgpu: Don't skip display settings in hwmgr_resume()

Maarten Lankhorst (16):
drm/atomic: Create __drm_atomic_helper_crtc_reset() for
subclassing crtc_state.
drm/docs: Fix typo in __drm_atomic_helper_connector_reset
drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper.
drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset.
drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset.
drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset.
drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.
drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
drm/i915: Nuke atomic set/get prop plane stubs
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next
Merge branch 'topic/remove-fbcon-notifiers' into drm-misc-next
Merge remote-tracking branch 'drm/drm-next' into drm-misc-next-fixes
Merge tag 'topic/remove-fbcon-notifiers-2019-06-26' into
drm-misc-next-fixes

Marco Felsch (4):
dt-bindings: display: add EDT ET035012DM6 display description
dt-bindings: Add vendor prefix for Evervision Electronics
dt-bindings: Add Evervision VGG804821 panel
drm/panel: simple: Add Evervision VGG804821 panel support

Marek Olšák (5):
drm/amdgpu: bump the DRM version for GDS ENOMEM fixes
drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)
drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)
drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10
drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback

Marek Vasut (2):
dt-bindings: display: Add ETM0430G0DH6 bindings
drm/panel: Add support for EDT ETM0430G0DH6

Markus Elfring (2):
drm/amd/display: Delete a redundant memory setting in
amdgpu_dm_irq_register_interrupt()
drm/amd/powerplay: Delete a redundant memory setting in
vega20_set_default_od8_setttings()

Martin Leung (1):
drm/amd/display: removing MODULO change for dcn2

Matt Roper (4):
drm/i915/ehl: Support HBR3 on EHL combo PHY
drm/i915: Add Wa_1409120013:icl,ehl
drm/i915/ehl: Update MOCS table for EHL
drm/i915/ehl: Introduce Mule Creek Canyon PCH

Matthew Auld (2):
drm/i915/gtt: grab wakeref in gen6_alloc_va_range
drm/i915: add in-kernel blitter client

Matthias Kaehlcke (1):
dt-bindings: gpu: add #cooling-cells property to the ARM Mali
Midgard GPU binding

Mauro Carvalho Chehab (2):
Documentation/i915: Fix references to renamed files
gpu: amdgpu: fix broken amdgpu_dma_buf.c references

Maxime Ripard (21):
drm/rockchip: Change the scl_vop_cal_scl_fac to pass drm_format_info
drm: Remove users of drm_format_num_planes
drm: Remove users of drm_format_(horz|vert)_chroma_subsampling
drm/fourcc: Pass the format_info pointer to drm_format_plane_cpp
drm/fourcc: Pass the format_info pointer to drm_format_plane_width/height
drm: Replace instances of drm_format_info by drm_get_format_info
drm: Remove users of drm_format_info_plane_cpp
drm/fourcc: Fix the parameters name in the documentation
dt-bindings: display: Convert Allwinner DSI to a schema
drm/connector: Add documentation for drm_cmdline_mode
drm/client: Restrict the plane_state scope
drm/client: Restrict the rotation check to the rotation itself
drm/client: Change drm_client_panel_rotation name
drm/modes: Rewrite the command line parser
drm/modes: Support modes names on the command line
drm/modes: Allow to specify rotation and reflection on the commandline
drm/connector: Introduce a TV margins structure
drm/modes: Parse overscan properties
drm/atomic: Add a function to reset connector TV properties
drm/selftests: Add command line parser selftests
drm/vc4: hdmi: Set default state margin at reset

Michal Wajdeczko (23):
drm/i915/selftests: Move some reset testcases to separate file
drm/i915/selftests: Split igt_atomic_reset testcase
drm/i915/selftests: Use prepare/finish during atomic reset test
drm/i915/guc: Rename intel_guc_is_alive to intel_guc_is_loaded
drm/i915/uc: Explicitly sanitize GuC/HuC on failure and finish
drm/i915/uc: Use GuC firmware status helper
drm/i915/uc: Skip GuC HW unwinding if GuC is already dead
drm/i915/uc: Stop talking with GuC when resetting
drm/i915/uc: Skip reset preparation if GuC is already dead
drm/i915/guc: Change platform default GuC mode
drm/i915/guc: Don't allow GuC submission
drm/i915/guc: Updates for GuC 32.0.3 firmware
drm/i915/guc: Reset GuC ADS during sanitize
drm/i915/guc: Always ask GuC to update power domain states
drm/i915/guc: Define GuC firmware version for Geminilake
drm/i915/huc: Define HuC firmware version for Geminilake
drm/i915/guc: New GuC interrupt register for Gen11
drm/i915/guc: New GuC scratch registers for Gen11
drm/i915/huc: New HuC status register for Gen11
drm/i915/guc: Update GuC CTB response definition
drm/i915/guc: Enable GuC CTB communication on Gen11
drm/i915/guc: Define GuC firmware version for Icelake
drm/i915/huc: Define HuC firmware version for Icelake

Mika Kuoppala (5):
drm/i915/gtt: No need to zero the table for page dirs
drm/i915/gtt: Use a common type for page directories
drm/i915/gtt: Introduce init_pd_with_page
drm/i915/gtt: Introduce init_pd
drm/i915/gtt: Generalize alloc_pd

Monk Liu (2):
drm/amdgpu: suppress repeating tmo report
drm/amdgpu: drop the incorrect soft_reset for SRIOV

Nathan Chancellor (5):
drm/msm/dsi: Add parentheses to quirks check in
dsi_phy_hw_v3_0_lane_settings
drm/amdgpu/mes10.1: Fix header guard
drm/amd/powerplay: Use memset to initialize metrics structs
drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq
drm/amd/powerplay: Zero initialize current_rpm in
vega20_get_fan_speed_percent

Nathan Huckleberry (1):
drm/msm/dpu: Fix Wunused-const-variable

Neil Armstrong (2):
drm/meson: Add zpos immutable property to planes
drm/meson: Add support for XBGR8888 & ABGR8888 formats

Nicholas Kazlauskas (23):
drm/amd/display: Fill prescale_params->scale for RGB565
drm/amd/display: Disable cursor when offscreen in negative direction
drm/amd/display: Hook up CRC capture support for dce120
drm/amd/display: Explicitly specify update type per plane info change
drm/amd/display: Switch the custom "max bpc" property to the DRM prop
drm/amd/display: Use new connector state when getting color depth
drm/amd/display: Reset planes for color management changes
drm/amd/display: Expose HDR output metadata for supported connectors
drm/amd/display: Only force modesets when toggling HDR
drm/amd/display: Don't set mode_changed=false if the stream was removed
drm/amd/display: Add back missing hw translate init for DCN1_01
drm/amd/display: Add connector debugfs for "output_bpc"
drm/amd/display: Always allocate initial connector state state
drm/amd/display: Use current connector state if NULL when checking bpc
drm/amd/display: Enable fast plane updates when
state->allow_modeset = true
drm/amdgpu: Add module parameter for specifying default ABM level
drm/amd/display: Set default ABM level to module parameter
drm/amd/display: Copy stream updates onto streams
drm/amd/display: Rework CRTC color management
Revert "drm/amd/display: Enable fast plane updates when
state->allow_modeset = true"
drm/amd/display: Copy stream updates onto streams
drm/amd/display: Rework CRTC color management
drm/amd/display: update infoframe after dig fe is turned on (v2)

Nicholas Mc Guire (1):
drm/msm: check for equals 0 only

Nikola Cornij (13):
drm/amd/display: Calculate link bandwidth in a common function
drm/amd/display: Remove additional FEC link bandwidth reduction
drm/amd/display: Use 1/8th DSC target bitrate precision for
N4:2:2 and 4:2:0 formats
drm/amd/display: Make sure DSC slice height is divisible by 2
for 4:2:0 color format
drm/amd/display: Mark DSC resource as unused after copying to
the secondary ODM pipe
drm/amd/display: Acquire DSC HW resource only if required by stream
drm/amd/display: Consider DSC target bpp precision when
calculating DSC target bpp
drm/amd/display: Make sure line size is not zero in DCN2 line
buffer size calculations
drm/amd/display: Add 170Mpix/sec DSC throughput support
drm/amd/display: Do a reg update instead of set when writing ODM
color format
drm/amd/display: Add support for extended DSC DPCD caps
drm/amd/display: Disable DSC power gating in Diags
drm/amd/display: Enable DSC power-gating for DSC streams

Noralf Trønnes (12):
drm/fb-helper: Avoid race with DRM userspace
drm/fb-helper: No need to cache rotation and sw_rotations
drm/fb-helper: Remove drm_fb_helper_crtc->{x, y, desired_mode}
drm/fb-helper: Fix drm_fb_helper_hotplug_event() NULL ptr argument
drm/fb-helper: Remove drm_fb_helper_crtc
drm/atomic: Move __drm_atomic_helper_disable_plane/set_config()
drm/fb-helper: Prepare to move out commit code
drm/fb-helper: Move out commit code
drm/fb-helper: Remove drm_fb_helper_connector
drm/fb-helper: Prepare to move out modeset config code
drm/fb-helper: Move out modeset config code
drm/todo: Add bootsplash entry

Oak Zeng (43):
drm/amdgpu: Remap hdp coherency registers
drm/amdkfd: Expose HDP registers to user space
drm/amdkfd: Use 64 bit sdma_bitmap
drm/amdkfd: Add sdma allocation debug message
drm/amdkfd: Differentiate b/t sdma_id and sdma_queue_id
drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd
drm/amdkfd: Introduce asic-specific mqd_manager_init function
drm/amdkfd: Introduce DIQ type mqd manager
drm/amdkfd: Init mqd managers in device queue manager init
drm/amdkfd: Add mqd size in mqd manager struct
drm/amdkfd: Allocate MQD trunk for HIQ and SDMA
drm/amdkfd: Fix a potential memory leak
drm/amdkfd: Move non-sdma mqd allocation out of init_mqd
drm/amdkfd: Allocate hiq and sdma mqd from mqd trunk
drm/amdkfd: Fix sdma queue map issue
drm/amdkfd: Introduce XGMI SDMA queue type
drm/amdkfd: Expose sdma engine numbers to topology
drm/amdkfd: Delete alloc_format field from map_queue struct
drm/amdkfd: Use kfd fd to mmap mmio
drm/amdkfd: Add gws number to kfd topology node properties
drm/amdgpu: Add interface to alloc gws from amdgpu
drm/amdkfd: Allocate gws on device initialization
drm/amdgpu: Add function to add/remove gws to kfd process
drm/amdkfd: Add function to set queue gws
drm/amdkfd: New IOCTL to allocate queue GWS
drm/amdkfd: PM4 packets change to support GWS
drm/amdkfd: Return proper error code for gws alloc API
drm/amdkfd: CP queue priority controls
drm/amdkfd: Only initialize sdma vm for sdma queues
drm/amdkfd: Only load sdma mqd when queue is active
drm/amdkfd: Refactor create_queue_nocpsch
drm/amdkfd: Separate mqd allocation and initialization
drm/amdkfd: Fix a circular lock dependency
drm/amdkfd: Fix sdma queue allocate race condition
drm/amdkfd: Initialize HSA_CAP_ATS_PRESENT capability in topology codes
drm/amdkfd: Add device to topology after it is completely inited
drm/amdgpu: Reserve space for shared fence
Revert "drm/amdkfd: Fix sdma queue allocate race condition"
Revert "drm/amdkfd: Fix a circular lock dependency"
drm/amdkfd: Fix a circular lock dependency
drm/amdkfd: Fix sdma queue allocate race condition
drm/amdkfd: Set gws_mask to 64 bit 1s
drm/amdgpu: Set queue_preemption_timeout_ms default value

Oleg Vasilev (3):
drm/i915: add i2c symlink under hdmi connector
drm: add debug print to update_vblank_count
drm/vkms: add crc sources list

Ori Messinger (1):
drm/amdgpu: Report firmware versions with sysfs v2

Oscar Mateo (2):
drm/i915/guc: Create vfuncs for the GuC interrupts control functions
drm/i915/guc: Correctly handle GuC interrupts on Gen11

Paul Cercueil (2):
dt-bindings: Add doc for the Ingenic JZ47xx LCD controller driver
DRM: Add KMS driver for the Ingenic JZ47xx SoCs

Paul Hsieh (3):
drm/amd/display: Disable ABM before destroy ABM struct
drm/amd/display: disable PSR/ABM before destroy DMCU struct
drm/amd/display: disable PSR/ABM before destroy DMCU struct

Paul Kocialkowski (5):
drm/sun4i: Use DRM_GEM_CMA_VMAP_DRIVER_OPS for GEM operations
drm/vc4: Reformat and the binner bo allocation helper
drm/vc4: Check for V3D before binner bo alloc
drm/vc4: Check for the binner bo before handling OOM interrupt
drm/vc4: Allocate binner bo when starting to use the V3D

Pawe? Chmiel (1):
drm/panel: Add driver for Samsung S6E63M0 panel

Peter Griffin (1):
drm/lima: handle shared irq case for lima_pp_bcast_irq_handler

Peter Ujfalusi (5):
dt-bindings: display: Add bindings for OSD101T2045-53TS
drm/panel: simple: Add support for OSD101T2045-53TS
dt-bindings: display: Add bindings for OSD101T2587-53TS panel
drm/panel: Add OSD101T2587-53TS driver
drm/panel: simple: Fix panel_simple_dsi_probe

Philip Cox (1):
drm/amdkfd: Add navi10 support to amdkfd. (v3)

Philip Yang (11):
drm: increase drm mmap_range size to 1TB
drm/amdgpu: use HMM callback to replace mmu notifier
drm/amdkfd: avoid HMM change cause circular lock
drm/amdgpu: replace get_user_pages with HMM mirror helpers
drm/amdgpu: fix HMM config dependency issue
drm/amdkfd: support concurrent userptr update for HMM
drm/amdgpu: support userptr cross VMAs case with HMM
drm/amdgpu: more descriptive message if HMM not enabled
drm/amdgpu: use new HMM APIs and helpers
drm/amdgpu: improve HMM error -ENOMEM and -EBUSY handling
drm/amdgpu: Prepare for hmm_range_register API change (v2)

Philipp Zabel (1):
drm/imx: enable IDMAC watermark feature

Philippe Cornu (1):
drm/stm: ltdc: use DRM_WARN for fifo & transfer error messages

Prike Liang (3):
drm/amd/amdgpu: add RLC firmware to support raven1 refresh
drm/amd/powerplay: detect version of smu backend (v2)
drm/amd/powerplay:clean up the residual mutex for smu_hw_init

Radhakrishna Sripada (1):
drm/i915/icl: Fix clockgating issue when using scalers

Ramalingam C (7):
drm: move content protection property to mode_config
drm/i915: debugfs: HDCP2.2 capability read
drm: generic fn converting be24 to cpu and vice versa
drm: revocation check at drm subsystem
drm/i915: SRM revocation check for HDCP1.4 and 2.2
drm/hdcp: gathering hdcp related code into drm_hdcp.c
drm/hdcp: drm_hdcp_request_srm() as static

Rex Zhu (4):
drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct
drm/amdgpu: Add common gfx func Disable kcq via kiq
drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_exec
drm/amdgpu: Add new ring interface preempt_ib

Rob Clark (1):
drm/msm/a3xx: remove TPL1 regs from snapshot

Rob Herring (1):
drm/panfrost: Align GEM objects GPU VA to 2MB

Robert Foss (1):
drm/virtio: Remove redundant return type

Robert M. Fosha (1):
drm/i915: Update workarounds selftest for read only regs

Rodrigo Siqueira (1):
drm/vkms: Remove useless call to drm_connector_register/unregister()

Roman Li (2):
drm/amd/display: Fill plane attrs only for valid pxl format
drm/amd/display: Fix null-deref on vega20 with xgmi

Russell King (30):
drm/armada: fix crtc interlace
drm/armada: use __drm_atomic_helper_plane_reset in overlay reset
drm/armada: add plane size/location accessors
drm/armada: fix plane location and size for interlace
drm/armada: add missing interlaced support for overlay frame
drm/armada: move plane address and pitch calculation to atomic_check
drm/armada: add support for setting gamma
drm/armada: add comments about HWC32 cursor colour format
drm/armada: add drm_mode_set_crtcinfo() mode fixup
drm/armada: add and use definitions for RDREG4F
drm/armada: add drm_atomic_helper_shutdown() call in tear-down
drm/armada: add CRTC mode validation
drm/i2c: tda998x: introduce tda998x_audio_settings
drm/i2c: tda998x: implement different I2S flavours
drm/i2c: tda998x: improve programming of audio divisor
drm/i2c: tda998x: derive CTS_N value from aclk sample rate ratio
drm/i2c: tda998x: store audio port enable in settings
drm/i2c: tda998x: index audio port enable config by route type
drm/i2c: tda998x: configure both fields of AIP_CLKSEL together
drm/i2c: tda998x: move audio routing configuration
drm/i2c: tda998x: clean up tda998x_configure_audio()
drm/i2c: tda998x: get rid of params in audio settings
drm/i2c: tda998x: add support for pixel repeated modes
drm/i2c: tda998x: improve correctness of quantisation range
drm/i2c: tda998x: add vendor specific infoframe support
drm/armada: improve Dove clock selection
drm/armada: use mode_valid to validate the adjusted mode
drm/armada: redo CRTC debugfs files
drm/armada: use for_each_endpoint_of_node() to walk crtc endpoints
drm/armada: no need to check parent of remote

Sabyasachi Gupta (1):
drm/bridge: Remove duplicate header

Sam Bobroff (1):
drm/bochs: Fix connector leak during driver unload

Sam Ravnborg (43):
drm: drop drm_bus from todo
drm/gma500: remove empty gma_drm.h header file
drm/gma500: drop drmP.h from header files
drm/gma500: make local header files more self-contained
drm/gma500: drop use of DRM_UDELAY wrapper
drm/gma500: drop drmp.h include from all .c files
drm/bridge: make dw_mipi_dsi.h self-contained
drm/bridge: drop drmP.h usage
drm/mcde: Fix compile problems
drm: make drm/drm_auth.h self contained
drm: make drm/drm_legacy.h self-contained
drm: make drm_crtc_internal.h self-contained
drm: make drm_internal.h self-contained
drm: make drm_legacy.h self-contained
drm: make drm_trace.h self-contained
drm: drop use of drmP.h in drm/*
drm/panel: panel-innolux: drop unused variable
drm/panel: drop drmP.h usage
drm/sis: drop drmP.h use
drm/savage: drop use of drm_os_linux
drm/savage: drop use of drmP.h
drm/r128: drop drm_os_linux dependencies
drm/r128: drop use of drmP.h
drm/sti: drop use of drmP.h
drm: drm_crtc.h self-contained
drm: drm_debugfs.h self-contained
drm/radeon: drop dependency on drm_os_linux.h
drm/radeon: drop drmP.h from header files
drm/radeon: prepare header files for drmP.h removal
drm/radeon: drop use of drmP.h (1/2)
drm/radeon: drop use of drmP.h (2/2)
drm: fix build errors with drm_print.h
drm/amd: drop dependencies on drm_os_linux.h
drm/amd: drop use of drmp.h in os_types.h
drm/amd: drop use of drmP.h in amdgpu.h
drm/amd: drop use of drmP.h in atom.h
drm/amd: drop use of drmP.h from all header files
drm/amd: drop use of drmP.h in powerplay/
drm/amd: drop use of drmP.h in display/
drm/amd: drop use of drmP.h in amdgpu/amdgpu*
drm/amd: drop use of drmP.h in remaining files
drm/exynos: drop drmP.h usage
drm/exynos: trigger build of all modules

Samson Tam (3):
drm/amd/display: block passive dongle EDID Emulation for USB-C ports
drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect
drm/amd/display: block passive dongle EDID Emulation for USB-C ports

Sandeep Sheriker Mallikarjun (2):
drm: atmel-hlcdc: enable sys_clk during initalization.
drm: atmel-hlcdc: add sam9x60 LCD controller

Sandor Yu (1):
drm/rockchip: cdn-dp: correct rate in the struct drm_dp_link assignment

Sean Paul (36):
Merge drm/drm-next into drm-misc-next
drm/mediatek: Fix warning about unhandled enum value
drm/edid: Fix docbook in drm_hdmi_infoframe_set_hdr_metadata()
drm/msm/a6xx: Avoid freeing gmu resources multiple times
drm/msm/a6xx: Remove duplicate irq disable from remove
drm/msm/a6xx: Check for ERR or NULL before iounmap
drm/msm/a6xx: Remove devm calls from gmu driver
drm/msm/a6xx: Drop the device reference in gmu
drm/msm/a6xx: Rename a6xx_gmu_probe to a6xx_gmu_init
drm: Tweak drm_encoder_helper_funcs.enable kerneldoc
drm: Add atomic variants of enable/disable to encoder helper funcs
drm: Add atomic variants for bridge enable/disable
drm: Convert connector_helper_funcs->atomic_check to accept
drm_atomic_state
drm: Add helpers to kick off self refresh mode in drivers
drm/rockchip: Use dirtyfb helper
drm/connector: Fix kerneldoc warning in HDR_OUTPUT_METADATA description
drm/amdgpu: Fix connector atomic_check compilation fail
drm/rcar-du: Fix error check when retrieving crtc state
drm/msm/dpu: Use provided drm_minor to initialize debugfs
drm/msm/dpu: Remove _dpu_debugfs_init
drm/msm/dpu: Remove bogus comment
drm/self_refresh: Fix possible NULL deref in failure path
drm/msm/dpu: Remove call to drm_mode_set_crtcinfo
drm/msm/dpu: Avoid calling _dpu_kms_mmu_destroy() on init failure
drm/msm/phy/dsi_phy: Set pll to NULL in case initialization fails
drm/msm/dsi_pll_10nm: Release clk hw on destroy and failure
drm/msm/dsi_pll_10nm: Remove impossible check
drm/msm: Depopulate platform on probe failure
drm/msm/dsi: Split mode_flags out of msm_dsi_host_get_panel()
drm/msm/dsi: Don't store dsi host mode_flags in msm_dsi
drm/msm/dsi: Pull out panel init code into function
drm/msm/dsi: Simplify the logic in msm_dsi_manager_panel_init()
drm/msm/dsi: Use the new setup_encoder function in attach_dsi_device
drm/msm/dsi: Move dsi panel init into modeset init path
drm/msm/dsi: Move setup_encoder to modeset_init
drm/msm: Re-order uninit function to work during probe defer

Sebastian Reichel (4):
drm/omap: use DRM_DEBUG_DRIVER instead of CORE
drm/omap: don't check dispc timings for DSI
drm/omap: add framedone interrupt support
drm/omap: add support for manually updated displays

Serge Semin (1):
drm: Permit video-buffers writecombine mapping for MIPS

Shashank Sharma (3):
drm/i915: Change gamma/degamma_lut_size data type to u32
drm/i915: Rename ivb_load_lut_10_max
drm/i915/icl: Add Multi-segmented gamma support

Shirish S (1):
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc

SivapiriyanKumarasamy (2):
drm/amd/display: Remove DPMS state dependency for fast boot
drm/amd/display: S3 Resume time increase after decoupling DPMS
from fast boot

Slava Abramov (1):
drm/amdgpu: use div64_ul for 32-bit compatibility v1

Souptick Joarder (1):
drm/panel: Remove duplicate header

Stanislav Lisovskiy (1):
drm/i915: Corrupt DSI picture fix for GeminiLake

Stephen Rothwell (1):
dt-bindings: fix up for vendor prefixes file conversion

Steve Longerbeam (6):
gpu: ipu-v3: ipu-ic: Fix saturation bit offset in TPMEM
gpu: ipu-v3: ipu-ic: Fully describe colorspace conversions
gpu: ipu-v3: ipu-ic-csc: Add support for limited range encoding
gpu: ipu-v3: ipu-ic-csc: Add support for Rec.709 encoding
media: imx: Try colorimetry at both sink and source pads
gpu: ipu-v3: image-convert: Enable double write reduction

Stuart Summers (5):
drm/i915: Use local variable for SSEU info in GETPARAM ioctl
drm/i915: Add macro for SSEU stride calculation
drm/i915: Move calculation of subslices per slice to new function
drm/i915: Refactor sseu helper functions
drm/i915: Expand subslice mask

Su Sung Chung (4):
drm/amd/display: fix calculation of total_data_read_bandwidth
drm/amd/display: fix crash on setmode when mode is close to bw limit
drm/amd/display: make clk_mgr call enable_pme_wa
drm/amd/display: make clk_mgr call enable_pme_wa

Swati Sharma (2):
drm/i915: Introduce vfunc read_luts() to create hw lut
drm/i915: Enable intel_color_get_config()

Sébastien Szymanski (1):
drm/panel: Add support for Armadeus ST0700 Adapt

Tao Zhou (5):
drm/amdgpu: Add psp 11.0 support for navi10.
drm/amd/powerplay/smu11: enable ds socclk by default
drm/amd/powerplay/smu11: add secure board check function (v2)
drm/amd/powerplay/smu11: disable some pp features on navi10 A0
secure board
drm/amdgpu: correct reference clock value on navi10

Tao.Huang (1):
drm/amd/display: fix resource saving missing when power state switch

Thierry Reding (6):
MAINTAINERS: Add Sam as reviewer for drm/panel
gpu: host1x: Do not output error message for deferred probe
gpu: host1x: Increase maximum DMA segment size
gpu: host1x: Do not link logical devices to DT nodes
drm/tegra: Use GPIO descriptor API
drm/tegra: dpaux: Make VDD supply optional

Thomas Hellstrom (11):
drm/vmwgfx: Assign eviction priorities to resources
mm: Allow the [page|pfn]_mkwrite callbacks to drop the mmap_sem
mm: Add an apply_to_pfn_range interface
mm: Add write-protect and clean utilities for address space ranges
drm/ttm: Allow the driver to provide the ttm struct vm_operations_struct
drm/ttm: TTM fault handler helpers
drm/vmwgfx: Implement an infrastructure for write-coherent resources
drm/vmwgfx: Use an RBtree instead of linked list for MOB resources
drm/vmwgfx: Implement an infrastructure for read-coherent resources
drm/vmwgfx: Add surface dirty-tracking callbacks
drm/vmwgfx: Kill unneeded legacy security features

Thomas Lim (3):
drm/amd/display: Add Underflow Asserts to dc
drm/amd/display: Add power down display on boot flag
drm/amd/display: Add Underflow Asserts to dc

Thomas Meyer (1):
drm/omap: Make sure device_id tables are NULL terminated

Thomas Zimmermann (36):
drm: Add |struct drm_gem_vram_object| and helpers
drm: Add |struct drm_gem_vram_object| callbacks for |struct ttm_bo_driver|
drm: Add |struct drm_gem_vram_object| callbacks for |struct drm_driver|
drm: Add drm_gem_vram_fill_create_dumb() to create dumb buffers
drm: Add simple PRIME helpers for GEM VRAM
drm: Add VRAM MM, a simple memory manager for dedicated VRAM
drm: Add default instance for VRAM MM callback functions
drm: Integrate VRAM MM into struct drm_device
drm/ast: Convert AST driver to |struct drm_gem_vram_object|
drm/ast: Convert AST driver to VRAM MM
drm/ast: Replace mapping code with drm_gem_vram_{kmap/kunmap}()
drm/bochs: Convert bochs driver to |struct drm_gem_vram_object|
drm/bochs: Convert bochs driver to VRAM MM
drm/mgag200: Convert mgag200 driver to |struct drm_gem_vram_object|
drm/mgag200: Convert mgag200 driver to VRAM MM
drm/mgag200: Replace mapping code with drm_gem_vram_{kmap/kunmap}()
drm/vboxvideo: Convert vboxvideo driver to |struct drm_gem_vram_object|
drm/vboxvideo: Convert vboxvideo driver to VRAM MM
drm/hisilicon: Convert hibmc-drm driver to |struct drm_gem_vram_object|
drm/hisilicon: Convert hibmc-drm driver to VRAM MM
drm: Add drm_gem_vram_{pin/unpin}_reserved() and convert mgag200
drm: Reserve/unreserve GEM VRAM BOs from within pin/unpin functions
drm: Replace drm_gem_vram_push_to_system() with kunmap + unpin
drm: Rename reserve/unreserve to lock/unlock in GEM VRAM helpers
drm: Assert that BO is locked in drm_gem_vram_{pin, unpin}_locked()
drm: Ignore drm_gem_vram_mm_funcs in generated documentation
drm: Reverse lock order in pan_display_legacy()
drm/gem-vram: Support pinning buffers to current location
drm/ast: Unpin cursor BO during cleanup
drm/ast: Remove obsolete or unused cursor state
drm/ast: Pin and map cursor source BO during update
drm/ast: Pin framebuffer BO during dirty update
drm/mgag200: Pin framebuffer BO during dirty update
drm/mgag200: Rewrite cursor handling
drm: Remove lock interfaces from GEM VRAM helpers
drm: Remove functions with kmap-object argument from GEM VRAM helpers

Tianci Yin (2):
drm/amdgpu/gfx10: update gfx golden settings
drm/amdgpu: disable some gfx light sleep

Tiecheng Zhou (1):
drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

Tom St Denis (6):
drm/amd/amdgpu: Add MEM_LOAD to amdgpu_pm_info debugfs file
drm/amd/doc: Add XGMI sysfs documentation
drm/amd/doc: Add RAS documentation to guide
drm/amd/amdgpu: remove vram_page_split kernel option (v3)
drm/amd/amdgpu: Bail out of BO node creation if not enough VRAM (v3)
drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting (v2)

Tomi Valkeinen (27):
drm/bridge: tc358767: fix tc_aux_get_status error handling
drm/bridge: tc358767: reset voltage-swing & pre-emphasis
drm/bridge: tc358767: fix ansi 8b10b use
drm/bridge: tc358767: cleanup spread & scrambler_dis
drm/bridge: tc358767: remove unused swing & preemp
drm/bridge: tc358767: cleanup aux_link_setup
drm/bridge: tc358767: move video stream setup to tc_main_link_stream
drm/bridge: tc358767: split stream enable/disable
drm/bridge: tc358767: move PXL PLL enable/disable to stream enable/disable
drm/bridge: tc358767: add link disable function
drm/bridge: tc358767: disable only video stream in tc_stream_disable
drm/bridge: tc358767: ensure DP is disabled before LT
drm/bridge: tc358767: remove unnecessary msleep
drm/bridge: tc358767: use more reliable seq when finishing LT
drm/bridge: tc358767: cleanup LT result check
drm/bridge: tc358767: clean-up link training
drm/bridge: tc358767: remove check for video mode in link enable
drm/bridge: tc358767: use bridge mode_valid
drm/bridge: tc358767: remove tc_connector_best_encoder
drm/bridge: tc358767: copy the mode data, instead of storing the pointer
drm/bridge: tc358767: read display_props in get_modes()
drm/bridge: tc358767: add GPIO & interrupt registers
drm/bridge: tc358767: add IRQ and HPD support
dt-bindings: tc358767: add HPD support
drm/bridge: sii902x: add input_bus_flags
drm/bridge: tfp410: fix memleak in get_modes()
drm/bridge: tfp410: fix use of cancel_delayed_work_sync

Tony Cheng (1):
drm/amd/display: move dsc clock from plane_resource to stream_resource

Trigger Huang (11):
drm/amdgpu: init vega10 SR-IOV reg access mode
drm/amdgpu: initialize PSP before IH under SR-IOV
drm/amdgpu: Add new PSP cmd GFX_CMD_ID_PROG_REG
drm/amdgpu: implement PSP cmd GFX_CMD_ID_PROG_REG
drm/amdgpu: call psp to program ih cntl in SR-IOV
drm/amdgpu: Support PSP VMR ring for Vega10 VF
drm/amdgpu: Skip setting some regs under Vega10 VF
drm/amdgpu: add basic func for RLC program reg
drm/amdgpu: RLC to program regs for Vega10 SR-IOV
drm/amdgpu: Hardcode reg access using L1 security
drm/amdgpu: fix pm_load_smu_firmware for SR-IOV

Tvrtko Ursulin (27):
drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
drm/i915/selftests: Verify context workarounds
drm/i915/icl: Add WaDisableBankHangMode
drm/i915: Engine discovery query
drm/i915: Reset only affected engines when handling error capture
drm/i915: Tidy engine mask types in hangcheck
drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
drm/i915: Extract engine fault reset to a helper
drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
drm/i915: Convert some more bits to use engine mmio accessors
drm/i915: Tidy intel_execlists_submission_init
drm/i915: Move i915_check_and_clear_faults to intel_reset.c
drm/i915: Eliminate unused mmio accessors
drm/i915: Convert i915_reg_read_ioctl to use explicit mmio accessors
drm/i915: Convert icl_get_stolen_reserved to uncore mmio accessors
drm/i915: Convert gem_record_fences to uncore mmio accessors
drm/i915: Convert intel_read_wm_latency to uncore mmio accessors
drm/i915: Remove I915_READ64 and I915_READ64_32x2
drm/i915: Make read_subslice_reg take engine
drm/i915/guc: Move intel_guc_reserved_gtt_size to intel_wopcm_guc_size
drm/i915: Make GuC GGTT reservation work on ggtt
drm/i915: Remove I915_READ8
drm/i915: Remove I915_POSTING_READ_FW
drm/i915: Remove POSTING_READ16
drm/i915: Remove I915_WRITE_NOTRACE
drm/i915: Remove I915_READ_NOTRACE
drm/i915: Remove I915_READ16 and I915_WRITE16

Tyler DiBattista (2):
drm/amd/display: Change Min fclk to 1.2Ghz
drm/amd/display: move DWB structs and enums to dc_hw_types

Uma Shankar (15):
drm: Add HDR source metadata property
drm: Parse HDR metadata info from EDID
drm: Enable HDR infoframe support
video/hdmi: Add Unpack function for DRM infoframe
drm/i915: Enabled Modeset when HDR Infoframe changes
drm/i915: Add DRM Infoframe handling for BYT/CHT
drm/i915: Write HDR infoframe and send to panel
drm/i915: Add state readout for DRM infoframe
drm/i915: Attach HDR metadata property to connector
drm: Drop a redundant unused variable
drm: Fixed doc warnings in drm uapi header
drm: ADD UAPI structure definition section in kernel doc
drm: Fix docbook warnings in hdr metadata helper structures
video/hdmi: Dropped static functions from kernel doc
drm/i915/icl: Add register definitions for Multi Segmented gamma

Vandita Kulkarni (4):
drm/i915: Fix the pipe state timing mismatch warnings
drm/i915: Refactor bdw_get_pipemisc_bpp
drm/i915: Fix pipe config mismatch for bpp, output format
drm/i915: Fix pixel clock and crtc clock config mismatch

Ville Syrjälä (70):
drm/i915: Fix skl+ max plane width
drm/i915: Fix ICL output CSC programming
drm/i915: Clean up cherryview_load_luts()
drm/i915: Flatten and rename haswell_set_pipemisc()
drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
drm/i915: Don't skip audio enable if ELD is bogus
drm/i915: hsw+ audio regs are per-transocder
drm/i915: Move the PIPEMISC write the correct place
drm/i915: Allow ICL pipe "HDR mode" when the cursor is visible
drm/i915: Use mul_u32_u32() more
drm/i915: Document that we implement WaIncreaseLatencyIPCEnabled
drm/i915: Drop WaIncreaseLatencyIPCEnabled/1140 for cnl
drm/i915: Move w/a 0477/WaDisableIPC:skl into intel_init_ipc()
drm/i915: Replace intel_ddi_pll_init()
drm/i915: Move the hsw/bdw pc8 code to intel_runtime_pm.c
drm/i915: Kill PCH_KBP
drm/i915: Fix fastset vs. pfit on/off on HSW EDP transcoder
drm/i915: Add readout and state check for pch_pfit.force_thru
drm/i915: Add a new "remapped" gtt_view
drm/i915/selftests: Add mock selftest for remapped vmas
drm/i915/selftests: Add live vma selftest
drm/i915: Shuffle stride checking code around
drm/i915: Overcome display engine stride limits via GTT remapping
drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+
drm/i915: Bump gen7+ fb size limits to 16kx16k
drm: Add HLG EOTF
drm/i915: Make sandybridge_pcode_read() deal with the second data register
drm/i915: Make sure we have enough memory bandwidth on ICL
drm/i915: Enable infoframes on GLK+ for HDR
drm/i915: Update pipe gamma enable bits when C8 planes are
getting enabled/disabled
drm/i915: Add debugs for the C8 vs. legacy LUT case
drm/i915: Pass intel_atomic_state to cdclk funcs
drm/i915: Clean up cdclk vfunc assignments
drm/i915: Pass intel_atomic state to check_digital_port_conflicts()
drm/i915: Use intel_ types in intel_modeset_clear_plls()
drm/i915: Use intel_ types in haswell_mode_set_planes_workaround()
drm/i915: Don't pass the crtc to intel_dump_pipe_config()
drm/i915: Don't pass the crtc to intel_modeset_pipe_config()
drm/i915: Use intel_ types in intel_modeset_checks()
drm/i915: Use intel_ types in intel_atomic_check()
drm/i915: Move state dump to the end of atomic_check()
drm/i915: Include crtc_state.active in crtc state dumps
drm/i915: Dump failed crtc states during atomic check
drm/i915: Make state dumpers take a const state
drm/i915: Fix plane state dumps
drm/edid: Clean up DRM_EDID_DIGITAL_* flags
drm/edid: Ignore "DFP 1.x" bit for EDID 1.2 and earlier
drm/i915: Move intel_dp->prepare_link_train assignment into ddi code
drm/i915: Drop pointless WARN_ON
drm/i915: Fix per-pixel alpha with CCS
drm/i915/sdvo: Fix AVI infoframe TX rate readout
drm/i915/sdvo: Implement proper HDMI audio support for SDVO
drm/i915: Rename SDVO_AUDIO_ENABLE to HDMI_AUDIO_ENABLE
drm/i915/sdvo: Check that we have space for the infoframe
drm/i915/sdvo: Don't unpack stack garbage
drm/i915/sdvo: Don't write stack garbage into the hbuf
drm/i915/sdvo: Actually print the reason why the SDVO command failed
drm/i915: Do not touch the PCH SSC reference if a PLL is using it
drm/i915: Rename HSW/BDW PLL bits
drm/i915: Nuke LC_FREQ
drm/i915: Assert that HSW/BDW LCPLL is using the non-SSC reference
drm/i915: Improve WRPLL reference clock readout on HSW/BDW
drm/i915: Add missing commas to the end of the subplatform ID arrays
drm/i915: Kill INTEL_SUBPLATFORM_AML
drm/dp: Add DP_DPCD_QUIRK_NO_SINK_COUNT
drm/i915: Don't clobber M/N values during fastset check
drm/i915: Constify intel_pipe_config_compare()
drm/i915: Make pipe_config_err() vs. fastset less confusing
drm/i915: Drop the _INCOMPLETE for has_infoframe

Vitaly Prosyak (6):
drm/amd/display: Reuse MPC OGRAM for 1D blender
drm/amd/display: Add a flags union for 3dlut transformation matrix
drm/amd/display: Add some tm3dlut flags
drm/amd/display: Add 3dlut control flags
drm/amd/display: add flags for gamut map library
drm/amd/display: Integrate color transform3x4 with 3dlut tm

Vivek Gautam (1):
drm/panel: truly: Add additional delay after pulling down reset gpio

Wang Hai (1):
drm/amd/display: Make some functions static

Weitao Hou (1):
gpu: fix typos in code comments

Wenjing Liu (11):
drm/amd/display: assign new stream id in dc_copy_stream
drm/amd/display: remove legacy DSC functions
drm/amd/display: remove target_dpp hack for dsc
drm/amd/display: isolate global double buffer lock programming
drm/amd/display: add global master update lock for DCN2
drm/amd/display: Implement DSC MST fair share algorithm
drm/amd/display: fix a potential issue in DSC logic
drm/amd/display: add dsc_passthrough_support bit in dpcd struct
drm/amd/display: decouple dsc adjustment out of enablement
drm/amd/display: update DSC MST DP virtual DPCD peer device
enumeration policy
drm/amd/display: update dsc max_target_bpp to 16 bpp

Wesley Chalmers (8):
drm/amd/display: Engine-specific encoder allocation
drm/amd/display: Use DCN functions instead of DCE
drm/amd/display: Update link rate from DPCD 10
drm/amd/display: Use macro for invalid OPP ID
drm/amd/display: Use stream opp_id instead of hubp
drm/amd/display: DCN2 Engine-specifc encoder allocation
drm/amd/display: Use DCN2 functions instead of DCE
drm/amd/display: Use macro for invalid OPP ID

Wolfram Sang (1):
gpu: drm: bridge: sii9234: simplify getting the adapter of a client

Xiaojie Yuan (15):
drm/amdgpu/discovery: add ip discovery initial support
drm/amdgpu/discovery: fix calculations of some gfx info
drm/amdgpu/discovery: update definitions of table_info and binary_header
drm/amdgpu/discovery: add harvest info data table
drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE
drm/amdgpu/discovery: fix hwid for nbio
drm/amdgpu/discovery: stop taking psp header into account
drm/amdgpu/discovery: update definition for struct die_header
drm/amdgpu/discovery: stop converting the units of base addresses
drm/amdgpu/discovery: add module param for ip discovery enablement
drm/amdgpu/discovery: refactor ip list traversal
drm/amdgpu/gfx10: fix resume failure when enabling async gfx ring
drm/amdgpu/gfx10: drop redundant se/sh selection
drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when
async_gfx_ring is disabled
drm/amd/display: use fixed-width data type for soc bounding box struct

Yannick Fertré (15):
drm/stm: ltdc: disable hw interrupts before its handler init
drm/stm: ltdc: fix data enable polarity
drm/stm: ltdc: update planes at next vblank to avoid partial refresh
drm/stm: ltdc: limit number of layer to avoid memory overflow
drm/stm: ltdc: reset controller to avoid partial refresh
drm/stm: ltdc: add modifier support
dt-bindings: display: stm32: add supply property to DSI controller
drm/stm: dsi: add regulator support
drm/stm: ltdc: remove clk_round_rate comment
drm/stm: dsi: check hardware version
drm/stm: ltdc: No message if probe
drm/stm: support runtime power management
drm/bridge/synopsys: dsi: add power on/off optional phy ops
drm/stm: dsi: add power on/off phy ops
drm/stm: drv: fix suspend/resume

Yintian Tao (1):
drm/amdgpu: register pm sysfs for sriov (v2)

Yogesh Mohan Marimuthu (1):
drm/amdgpu: sort probed modes before adding common modes

Yong Zhao (1):
drm/amdkfd: Move sdma_queue_id calculation into allocate_sdma_queue()

Yongqiang Sun (6):
drm/amd/display: Refactor program watermark.
drm/amd/display: DCN2 reg refactors
drm/amd/display: Remove REFCYC regs
drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUB
drm/amd/display: Refactor program watermark.
drm/amd/display: DCHUB requestors numbers for Navi.

Yrjan Skrimstad (1):
drm/amd/powerplay/smu7_hwmgr: replace blocking delay with non-blocking

abdoulaye berthe (1):
drm/amd/display: Do not grant POST_LT_ADJ when TPS4 is used

hersen wu (17):
drm/amd/powerplay: allow dc request uclk change
drm/amd/powerplay: notify smu with active display count
drm/amd/powerplay: wake up azalia from d3 by sending smu message
drm/amd/powerplay: add interface to get uclk dpm table
drm/amd/powerplay: allow dc request uclk change
drm/amd/powerplay: notify smu with active display count
drm/amd/powrplay: add interface for dc to get max clock values
drm/amd/powerplay: add interface to get uclk dpm table
drm/amd/display: hook navi10 pplib functions
drm/amd/display/dc: fix azalia workaround sw implementation bug
drm/amd/display: disable dcn20 abm feature for bring up
drm/amd/display: do not need otg lock if otg is not active
drm/amd/display: skip dsc config for navi10 bring up
drm/amd/display: navi10 bring up skip dsc encoder config
drm/amd/display: Add vupdate interrupt sources to NV10
drm/amd/display: Disable display writeback on Linux for NV10
drm/amd/display/dc: set num-dwb = 1 as navi10 asic cap

james qian wang (Arm Technology China) (21):
drm/komeda: Add writeback support
drm/komeda: Added AFBC support for komeda driver
drm/komeda: Attach scaler to drm as private object
drm/komeda: Add the initial scaler support for CORE
drm/komeda: Implement D71 scaler support
drm/komeda: Add writeback scaling support
drm/komeda: Add engine clock requirement check for the downscaling
drm/komeda: Add image enhancement support
drm/komeda: Add komeda_fb_check_src_coords
drm/komeda: Add format support for Y0L2, P010, YUV420_8/10BIT
drm/komeda: Unify mclk/pclk/pipeline->aclk to one MCLK
drm/komeda: Rename main engine clk name "mclk" to "aclk"
dt/bindings: drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK
drm/komeda: Add component komeda_merger
drm/komeda: Add split support for scaler
drm/komeda: Add layer split support
drm/komeda: Refine function to_d71_input_id
drm/komeda: Accept null writeback configurations for writeback
drm/komeda: Add new component komeda_splitter
drm/komeda: Enable writeback split support
drm/komeda: Correct printk format specifier for "size_t"

kbuild test robot (1):
drm/bochs: fix ptr_ret.cocci warnings

shaoyunl (5):
drm/amdgpu: Implement get num of hops between two xgmi device
drm/amdkfd: Adjust weight to represent num_hops info when report
xgmi iolink
drm/amdgpu: Update latest xgmi topology info after each device
is enumulated
drm/amdgpu: Use heavy weight for tlb invalidation on xgmi configuration
drm/amdkfd: remove unnecessary warning message on gpu reset

tiancyin (7):
drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test
drm/amd/powerplay: disable uclk dpm by default
drm/amdgpu/gfx10: update gfx golden settings
drm/amd/powerplay: add ppt interface version log
drm/amdgpu: add new navi10 DIDs
drm/amdgpu: disable gfxoff on navi10
drm/amd/powerplay: update smu11_driver_if_navi10.h

xinhui pan (18):
drm/amdgpu: gpu reset will run late_init
drm/amdgpu: Revert "drm/amdgpu: skip gpu reset when ras error occured"
drm/amdgpu: Issue ras TA disable/enable cmd forcely on boot
drm/amdgpu: handle ras reset
drm/amdgpu: gmc support ras gpu reset
drm/amdgpu: gfx support ras gpu reset
drm/amdgpu: sdma support ras gpu reset
drm/amdgpu: gpu reset will run ras post init
drm/amdgpu: add badpages sysfs interafce
drm/amdgpu: ras support suspend/resume
drm/amdgpu: enable ras suspend/resume
drm/amdgpu: gmc handle ras resume
drm/amdgpu: gfx handle ras resume
drm/amdgpu: sdma handle ras resume
drm/amdgpu: ras injection use gpu address
drm/amdgpu: cancel late_init_work before gpu reset
drm/amdgpu: Do error injection even vram reserve fails
drm/amdgpu: Disable ras features on all IPs before gpu reset

Documentation/arm64/sve.txt | 16 +
Documentation/block/switching-sched.txt | 18 +-
Documentation/cgroup-v1/blkio-controller.txt | 96 +-
Documentation/cgroup-v1/hugetlb.txt | 22 +-
.../display/allwinner,sun6i-a31-mipi-dsi.yaml | 100 +
.../devicetree/bindings/display/arm,komeda.txt | 23 +-
.../bindings/display/bridge/renesas,lvds.txt | 19 +-
.../devicetree/bindings/display/bridge/sii902x.txt | 42 +-
.../bindings/display/bridge/thine,thc63lvd1024.txt | 6 +
.../bindings/display/bridge/toshiba,tc358767.txt | 1 +
.../devicetree/bindings/display/ingenic,lcd.txt | 44 +
.../devicetree/bindings/display/msm/dpu.txt | 10 +
.../devicetree/bindings/display/msm/dsi.txt | 1 +
.../display/panel/armadeus,st0700-adapt.txt | 9 +
.../bindings/display/panel/edt,et-series.txt | 16 +
.../display/panel/evervision,vgg804821.txt | 12 +
.../bindings/display/panel/friendlyarm,hd702e.txt | 32 +
.../bindings/display/panel/koe,tx14d24vm1bpa.txt | 42 +
.../display/panel/osddisplays,osd101t2045-53ts.txt | 11 +
.../display/panel/osddisplays,osd101t2587-53ts.txt | 14 +
.../bindings/display/panel/samsung,s6e63m0.txt | 33 +
.../display/panel/tfc,s9700rtwv43tr-01b.txt | 15 +
.../bindings/display/panel/vl050_8048nt_c01.txt | 12 +
.../devicetree/bindings/display/renesas,du.txt | 2 +
.../bindings/display/rockchip/dw_hdmi-rockchip.txt | 8 +
.../devicetree/bindings/display/st,stm32-ltdc.txt | 3 +
.../bindings/display/sunxi/sun6i-dsi.txt | 93 -
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 19 +-
.../phy/allwinner,sun6i-a31-mipi-dphy.yaml | 57 +
.../devicetree/bindings/vendor-prefixes.yaml | 6 +
Documentation/fb/modedb.txt | 14 +
Documentation/gpu/amdgpu.rst | 24 +-
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/drm-client.rst | 3 +
Documentation/gpu/drm-kms-helpers.rst | 15 +
Documentation/gpu/drm-mm.rst | 34 +-
Documentation/gpu/drm-uapi.rst | 19 +-
Documentation/gpu/i915.rst | 87 +-
Documentation/gpu/mcde.rst | 8 +
Documentation/gpu/todo.rst | 55 +-
MAINTAINERS | 10 +-
Makefile | 2 +-
arch/arm64/Makefile | 2 +-
arch/arm64/include/asm/tlbflush.h | 3 +
arch/arm64/include/uapi/asm/kvm.h | 7 +
arch/arm64/include/uapi/asm/ptrace.h | 4 +
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drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 144 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 148 +-
drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 2 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 260 +-
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 75 +
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 93 +-
drivers/gpu/drm/amd/display/dc/dc.h | 144 +-
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 127 +
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 62 +
drivers/gpu/drm/amd/display/dc/dc_helper.c | 5 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 122 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 11 +
drivers/gpu/drm/amd/display/dc/dc_stream.h | 75 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 118 +-
drivers/gpu/drm/amd/display/dc/dce/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 15 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 20 +
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +-
drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 7 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 10 +
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 2 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 87 +-
.../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 42 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 97 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 10 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 127 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 109 +-
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 30 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c | 3 +
drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 3 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 +
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 16 +-
.../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 +-
.../drm/amd/display/dc/dce100/dce100_resource.c | 75 +-
.../drm/amd/display/dc/dce100/dce100_resource.h | 5 +
.../drm/amd/display/dc/dce110/dce110_compressor.c | 3 +
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 200 +-
.../amd/display/dc/dce110/dce110_opp_regamma_v.c | 2 +
.../drm/amd/display/dc/dce110/dce110_resource.c | 69 +-
.../drm/amd/display/dc/dce110/dce110_resource.h | 5 +
.../display/dc/dce110/dce110_timing_generator.c | 5 +
.../display/dc/dce110/dce110_timing_generator.h | 5 +
.../display/dc/dce110/dce110_timing_generator_v.c | 5 +
.../drm/amd/display/dc/dce110/dce110_transform_v.c | 2 +
.../drm/amd/display/dc/dce112/dce112_compressor.c | 3 +
.../drm/amd/display/dc/dce112/dce112_resource.c | 33 +-
.../drm/amd/display/dc/dce120/dce120_resource.c | 39 +-
.../display/dc/dce120/dce120_timing_generator.c | 96 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 52 +-
.../amd/display/dc/dce80/dce80_timing_generator.c | 7 +-
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h | 31 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 136 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 271 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 471 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 16 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 34 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 8 +
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 197 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +
.../display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 26 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 43 +
.../drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 11 +-
.../drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 174 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 6 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 10 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 213 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 91 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 74 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 5 +
.../amd/display/dc/dcn10/dcn10_stream_encoder.c | 129 +-
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 79 +
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 17 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 159 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 116 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 502 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 698 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 990 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 694 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 575 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 332 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h | 458 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 877 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 592 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 107 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 700 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 277 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2008 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 103 +
.../drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 460 +
.../drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 173 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c | 323 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h | 544 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 526 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h | 285 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 355 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 158 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 542 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 116 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3177 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 133 +
.../amd/display/dc/dcn20/dcn20_stream_encoder.c | 610 +
.../amd/display/dc/dcn20/dcn20_stream_encoder.h | 107 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 59 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 90 +
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 7 +
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 142 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 14 +-
.../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 5104 +
.../amd/display/dc/dml/dcn20/display_mode_vba_20.h | 32 +
.../display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 1701 +
.../display/dc/dml/dcn20/display_rq_dlg_calc_20.h | 74 +
.../drm/amd/display/dc/dml/display_mode_enums.h | 12 +-
.../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 22 +
.../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 36 +-
.../drm/amd/display/dc/dml/display_mode_structs.h | 32 +
.../gpu/drm/amd/display/dc/dml/display_mode_vba.c | 839 +
.../gpu/drm/amd/display/dc/dml/display_mode_vba.h | 854 +
.../gpu/drm/amd/display/dc/dml/dml_inline_defs.h | 8 +
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 13 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 858 +
drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c | 382 +
drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h | 54 +
drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h | 706 +
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 258 +
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 85 +
drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 147 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../amd/display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 +
.../amd/display/dc/gpio/dcn20/hw_factory_dcn20.h | 33 +
.../amd/display/dc/gpio/dcn20/hw_translate_dcn20.c | 382 +
.../amd/display/dc/gpio/dcn20/hw_translate_dcn20.h | 35 +
drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h | 53 +
drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c | 2 +
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 2 +
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 18 +
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 13 +-
drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 2 +
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 11 +-
drivers/gpu/drm/amd/display/dc/inc/core_status.h | 5 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 93 +-
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 7 +
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/audio.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 31 +-
.../dce_clk_mgr.h => inc/hw/clk_mgr_internal.h} | 220 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 58 +
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 70 +
drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 101 +
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 180 +
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 30 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 50 +-
.../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 28 +
drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 105 +
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 52 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 29 +
.../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 66 +-
.../drm/amd/display/dc/inc/hw/timing_generator.h | 60 +-
drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 58 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 8 +
drivers/gpu/drm/amd/display/dc/inc/vm_helper.h | 16 +-
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +
.../amd/display/dc/irq/dce120/irq_service_dce120.c | 2 +
.../amd/display/dc/irq/dce80/irq_service_dce80.c | 2 +
.../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 4 +-
.../amd/display/dc/irq/dcn20/irq_service_dcn20.c | 375 +
.../amd/display/dc/irq/dcn20/irq_service_dcn20.h | 34 +
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 +
drivers/gpu/drm/amd/display/dc/os_types.h | 8 +-
.../amd/display/dc/virtual/virtual_link_encoder.c | 2 +
.../display/dc/virtual/virtual_stream_encoder.c | 17 +
.../drm/amd/display/include/bios_parser_types.h | 3 +-
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 20 +-
drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
drivers/gpu/drm/amd/display/include/logger_types.h | 10 +
.../gpu/drm/amd/display/include/set_mode_types.h | 5 +-
.../drm/amd/display/modules/color/color_gamma.c | 62 +-
.../drm/amd/display/modules/color/color_gamma.h | 1 +
.../drm/amd/display/modules/freesync/freesync.c | 2 +
.../gpu/drm/amd/display/modules/inc/mod_shared.h | 60 +
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 46 +
.../amd/display/modules/info_packet/info_packet.c | 4 +-
drivers/gpu/drm/amd/display/modules/power/Makefile | 2 +-
drivers/gpu/drm/amd/display/modules/vmid/vmid.c | 167 +
drivers/gpu/drm/amd/include/amd_shared.h | 11 +-
.../include/asic_reg/athub/athub_2_0_0_default.h | 272 +
.../include/asic_reg/athub/athub_2_0_0_offset.h | 514 +
.../include/asic_reg/athub/athub_2_0_0_sh_mask.h | 2264 +
.../amd/include/asic_reg/clk/clk_11_0_0_offset.h | 33 +
.../amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h | 38 +
.../amd/include/asic_reg/dcn/dcn_2_0_0_offset.h | 17535 +++
.../amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 68024 ++++++++++
.../drm/amd/include/asic_reg/df/df_3_6_offset.h | 18 +
.../amd/include/asic_reg/gc/gc_10_1_0_default.h | 6028 +
.../drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 11339 ++
.../amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h | 43963 +++++++
.../drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 31 +
.../amd/include/asic_reg/hdp/hdp_5_0_0_offset.h | 217 +
.../amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h | 659 +
.../include/asic_reg/mmhub/mmhub_2_0_0_default.h | 927 +
.../include/asic_reg/mmhub/mmhub_2_0_0_offset.h | 1799 +
.../include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h | 7567 ++
.../drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h | 429 +
.../amd/include/asic_reg/nbio/nbio_2_3_default.h | 18521 +++
.../amd/include/asic_reg/nbio/nbio_2_3_offset.h | 14663 +++
.../amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h | 120339 ++++++++++++++++++
.../drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h | 3 +
.../drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h | 3 +
.../drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h | 3 +
.../amd/include/asic_reg/oss/osssys_5_0_0_offset.h | 353 +
.../include/asic_reg/oss/osssys_5_0_0_sh_mask.h | 1305 +
.../include/asic_reg/smuio/smuio_11_0_0_offset.h | 323 +
.../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h | 689 +
.../amd/include/asic_reg/vcn/vcn_2_0_0_offset.h | 1008 +
.../amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h | 3815 +
drivers/gpu/drm/amd/include/atomfirmware.h | 188 +-
drivers/gpu/drm/amd/include/cik_structs.h | 3 +-
drivers/gpu/drm/amd/include/discovery.h | 165 +
.../include/ivsrcid/{ => dcn}/irqsrcs_dcn_1_0.h | 0
.../drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h | 53 +
.../amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h | 43 +
.../amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h | 44 +
.../drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h | 32 +
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 1 +
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 11 +
drivers/gpu/drm/amd/include/navi10_enum.h | 22764 ++++
drivers/gpu/drm/amd/include/navi10_ip_offset.h | 855 +
drivers/gpu/drm/amd/include/soc15_hw_ip.h | 4 +-
drivers/gpu/drm/amd/include/v10_structs.h | 1258 +
drivers/gpu/drm/amd/include/v9_structs.h | 3 +-
drivers/gpu/drm/amd/include/vi_structs.h | 3 +-
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 425 +-
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 18 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +-
.../amd/powerplay/hwmgr/process_pptables_v1_0.c | 4 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 3 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 157 +-
.../amd/powerplay/hwmgr/vega10_processpptables.c | 25 +
.../amd/powerplay/hwmgr/vega10_processpptables.h | 1 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 123 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h | 3 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 84 +-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 361 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
drivers/gpu/drm/amd/powerplay/inc/power_state.h | 7 +
drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h | 12 +-
.../drm/amd/powerplay/inc/smu11_driver_if_navi10.h | 1069 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 29 +
.../gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 39 +-
.../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 2 +-
drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1579 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 28 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1232 +-
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 +
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 3 +
.../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 4 +
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 9 +
.../gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 3 +
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 1 +
.../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 4 +
.../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 3 +
.../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c | 22 +
.../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c | 1 +
.../gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 3 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1285 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 50 +
drivers/gpu/drm/arm/display/include/malidp_io.h | 7 +
drivers/gpu/drm/arm/display/include/malidp_utils.h | 5 +-
drivers/gpu/drm/arm/display/komeda/Makefile | 2 +
.../gpu/drm/arm/display/komeda/d71/d71_component.c | 582 +-
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c | 142 +-
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h | 2 +
.../gpu/drm/arm/display/komeda/komeda_color_mgmt.c | 67 +
.../gpu/drm/arm/display/komeda/komeda_color_mgmt.h | 17 +
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 154 +-
drivers/gpu/drm/arm/display/komeda/komeda_dev.c | 59 +-
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 13 +-
.../drm/arm/display/komeda/komeda_format_caps.c | 58 +
.../drm/arm/display/komeda/komeda_format_caps.h | 24 +-
.../drm/arm/display/komeda/komeda_framebuffer.c | 175 +-
.../drm/arm/display/komeda/komeda_framebuffer.h | 13 +-
drivers/gpu/drm/arm/display/komeda/komeda_kms.c | 130 +-
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kernel/memremap.c | 23 +-
kernel/ptrace.c | 20 +-
kernel/time/timekeeping.c | 5 +-
kernel/trace/ftrace.c | 22 +-
kernel/trace/trace.c | 4 +-
kernel/trace/trace_output.c | 2 +-
kernel/trace/trace_uprobe.c | 15 +-
lib/genalloc.c | 51 +-
mm/Kconfig | 3 +
mm/Makefile | 1 +
mm/as_dirty_helpers.c | 298 +
mm/hmm.c | 14 +-
mm/khugepaged.c | 3 +
mm/list_lru.c | 2 +-
mm/memcontrol.c | 41 +-
mm/memory.c | 145 +-
mm/mlock.c | 7 +-
mm/mmu_gather.c | 24 +-
mm/vmalloc.c | 14 +-
mm/vmscan.c | 6 +-
scripts/decode_stacktrace.sh | 2 +-
security/selinux/avc.c | 10 +-
security/selinux/hooks.c | 39 +-
security/smack/smack_lsm.c | 12 +-
sound/firewire/motu/motu-stream.c | 2 +-
sound/firewire/oxfw/oxfw.c | 3 -
sound/hda/ext/hdac_ext_bus.c | 1 -
sound/pci/hda/hda_codec.c | 9 +-
sound/pci/hda/patch_realtek.c | 91 +-
sound/pci/ice1712/ews.c | 2 +-
sound/soc/codecs/ak4458.c | 18 +-
sound/soc/codecs/cs4265.c | 2 +-
sound/soc/codecs/cs42xx8.c | 1 +
sound/soc/codecs/max98090.c | 16 +
sound/soc/codecs/rt274.c | 3 +-
sound/soc/codecs/rt5670.c | 12 +
sound/soc/codecs/rt5677-spi.c | 5 +-
sound/soc/fsl/fsl_asrc.c | 4 +-
sound/soc/intel/atom/sst/sst_pvt.c | 4 +-
sound/soc/intel/boards/bytcht_es8316.c | 2 +-
sound/soc/intel/boards/cht_bsw_max98090_ti.c | 2 +-
sound/soc/intel/boards/cht_bsw_nau8824.c | 2 +-
sound/soc/intel/boards/cht_bsw_rt5672.c | 2 +-
sound/soc/intel/boards/sof_rt5682.c | 11 +-
sound/soc/intel/common/soc-acpi-intel-byt-match.c | 17 +
sound/soc/intel/common/soc-acpi-intel-cnl-match.c | 10 +-
sound/soc/mediatek/Kconfig | 2 +-
sound/soc/soc-core.c | 36 +-
sound/soc/soc-dapm.c | 7 +-
sound/soc/soc-pcm.c | 3 +-
sound/soc/sof/Kconfig | 8 +-
sound/soc/sof/control.c | 9 +-
sound/soc/sof/core.c | 29 +-
sound/soc/sof/intel/bdw.c | 26 +-
sound/soc/sof/intel/byt.c | 25 +-
sound/soc/sof/intel/cnl.c | 4 +
sound/soc/sof/intel/hda-ctrl.c | 102 +-
sound/soc/sof/intel/hda-ipc.c | 17 +-
sound/soc/sof/intel/hda.c | 129 +-
sound/soc/sof/ipc.c | 26 +-
sound/soc/sof/loader.c | 2 +
sound/soc/sof/pcm.c | 8 +-
sound/soc/sof/xtensa/core.c | 2 +-
sound/soc/sunxi/sun4i-codec.c | 9 +
sound/soc/sunxi/sun4i-i2s.c | 6 +-
tools/testing/nvdimm/test/iomap.c | 2 +
1785 files changed, 479818 insertions(+), 36145 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/evervision,vgg804821.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/friendlyarm,hd702e.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/koe,tx14d24vm1bpa.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/osddisplays,osd101t2045-53ts.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/osddisplays,osd101t2587-53ts.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,s6e63m0.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/vl050_8048nt_c01.txt
delete mode 100644
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
create mode 100644
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
create mode 100644 Documentation/gpu/mcde.rst
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
rename drivers/gpu/drm/amd/amdgpu/{amdgpu_prime.c => amdgpu_dma_buf.c} (93%)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx10.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_ih.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_ih.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
rename drivers/gpu/drm/{i915/i915_gemfs.h => amd/amdgpu/nbio_v2_3.h} (52%)
create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nv.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nvd.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
create mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h
rename drivers/gpu/drm/amd/display/dc/{dcn10/dcn10_clk_mgr.c =>
clk_mgr/dcn10/rv1_clk_mgr.c} (59%)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.h
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
create mode 100644
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c
rename drivers/gpu/drm/amd/display/dc/{dcn10/dcn10_clk_mgr.h =>
clk_mgr/dcn10/rv2_clk_mgr.h} (82%)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
create mode 100644
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
create mode 100644
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.h
create mode 100644
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
create mode 100644
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
rename drivers/gpu/drm/amd/display/dc/{dce/dce_clk_mgr.h =>
inc/hw/clk_mgr_internal.h} (51%)
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
create mode 100644 drivers/gpu/drm/amd/display/modules/vmid/vmid.c
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_default.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_offset.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/athub/athub_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_offset.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
create mode 100644
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/discovery.h
rename drivers/gpu/drm/amd/include/ivsrcid/{ => dcn}/irqsrcs_dcn_1_0.h (100%)
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h
create mode 100644
drivers/gpu/drm/amd/include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h
create mode 100644
drivers/gpu/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h
create mode 100644 drivers/gpu/drm/amd/include/navi10_enum.h
create mode 100644 drivers/gpu/drm/amd/include/navi10_ip_offset.h
create mode 100644 drivers/gpu/drm/amd/include/v10_structs.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/navi10_ppt.h
create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.c
create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_color_mgmt.h
create mode 100644 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
delete mode 100644 drivers/gpu/drm/cirrus/cirrus_ttm.c
create mode 100644 drivers/gpu/drm/drm_client_modeset.c
create mode 100644 drivers/gpu/drm/drm_gem_vram_helper.c
create mode 100644 drivers/gpu/drm/drm_hdcp.c
create mode 100644 drivers/gpu/drm/drm_self_refresh_helper.c
create mode 100644 drivers/gpu/drm/drm_vram_helper_common.c
create mode 100644 drivers/gpu/drm/drm_vram_mm_helper.c
create mode 100644 drivers/gpu/drm/i915/Kconfig.profile
create mode 100644 drivers/gpu/drm/i915/display/Makefile
create mode 100644 drivers/gpu/drm/i915/display/Makefile.header-test
rename drivers/gpu/drm/i915/{ => display}/dvo_ch7017.c (99%)
rename drivers/gpu/drm/i915/{ => display}/dvo_ch7xxx.c (99%)
rename drivers/gpu/drm/i915/{ => display}/dvo_ivch.c (99%)
rename drivers/gpu/drm/i915/{ => display}/dvo_ns2501.c (99%)
rename drivers/gpu/drm/i915/{ => display}/dvo_sil164.c (99%)
rename drivers/gpu/drm/i915/{ => display}/dvo_tfp410.c (99%)
rename drivers/gpu/drm/i915/{ => display}/icl_dsi.c (89%)
rename drivers/gpu/drm/i915/{ => display}/intel_acpi.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_acpi.h
rename drivers/gpu/drm/i915/{ => display}/intel_atomic.c (93%)
create mode 100644 drivers/gpu/drm/i915/display/intel_atomic.h
rename drivers/gpu/drm/i915/{ => display}/intel_atomic_plane.c (88%)
rename drivers/gpu/drm/i915/{ => display}/intel_atomic_plane.h (77%)
rename drivers/gpu/drm/i915/{ => display}/intel_audio.c (95%)
rename drivers/gpu/drm/i915/{ => display}/intel_audio.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_bios.c (94%)
rename drivers/gpu/drm/i915/{ => display}/intel_bios.h (83%)
create mode 100644 drivers/gpu/drm/i915/display/intel_bw.c
create mode 100644 drivers/gpu/drm/i915/display/intel_bw.h
rename drivers/gpu/drm/i915/{ => display}/intel_cdclk.c (91%)
rename drivers/gpu/drm/i915/{ => display}/intel_cdclk.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_color.c (85%)
rename drivers/gpu/drm/i915/{ => display}/intel_color.h (87%)
rename drivers/gpu/drm/i915/{ => display}/intel_combo_phy.c (77%)
create mode 100644 drivers/gpu/drm/i915/display/intel_combo_phy.h
rename drivers/gpu/drm/i915/{ => display}/intel_connector.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_connector.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_crt.c (96%)
rename drivers/gpu/drm/i915/{ => display}/intel_crt.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_ddi.c (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_ddi.h (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_display.c (93%)
rename drivers/gpu/drm/i915/{ => display}/intel_display.h (79%)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power.c
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power.h
rename drivers/gpu/drm/i915/{ => display}/intel_dp.c (96%)
rename drivers/gpu/drm/i915/{ => display}/intel_dp.h (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_dp_aux_backlight.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
rename drivers/gpu/drm/i915/{ => display}/intel_dp_link_training.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_link_training.h
rename drivers/gpu/drm/i915/{ => display}/intel_dp_mst.c (98%)
create mode 100644 drivers/gpu/drm/i915/display/intel_dp_mst.h
rename drivers/gpu/drm/i915/{ => display}/intel_dpio_phy.c (98%)
create mode 100644 drivers/gpu/drm/i915/display/intel_dpio_phy.h
rename drivers/gpu/drm/i915/{ => display}/intel_dpll_mgr.c (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_dpll_mgr.h (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_dsi.c (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_dsi.h (95%)
rename drivers/gpu/drm/i915/{ => display}/intel_dsi_dcs_backlight.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
rename drivers/gpu/drm/i915/{ => display}/intel_dsi_vbt.c (70%)
rename drivers/gpu/drm/i915/{ => display}/intel_dvo.c (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_dvo.h (100%)
rename drivers/gpu/drm/i915/{dvo.h => display/intel_dvo_dev.h} (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_fbc.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_fbc.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_fbdev.c (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_fbdev.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_fifo_underrun.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_fifo_underrun.h
rename drivers/gpu/drm/i915/{ => display}/intel_frontbuffer.c (96%)
rename drivers/gpu/drm/i915/{ => display}/intel_frontbuffer.h (99%)
rename drivers/gpu/drm/i915/{intel_i2c.c => display/intel_gmbus.c} (91%)
create mode 100644 drivers/gpu/drm/i915/display/intel_gmbus.h
rename drivers/gpu/drm/i915/{ => display}/intel_hdcp.c (96%)
rename drivers/gpu/drm/i915/{ => display}/intel_hdcp.h (94%)
rename drivers/gpu/drm/i915/{ => display}/intel_hdmi.c (95%)
rename drivers/gpu/drm/i915/{ => display}/intel_hdmi.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_hotplug.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_hotplug.h
rename drivers/gpu/drm/i915/{ => display}/intel_lpe_audio.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_lpe_audio.h
rename drivers/gpu/drm/i915/{ => display}/intel_lspcon.c (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_lspcon.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_lvds.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_lvds.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_opregion.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_opregion.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_overlay.c (98%)
create mode 100644 drivers/gpu/drm/i915/display/intel_overlay.h
rename drivers/gpu/drm/i915/{ => display}/intel_panel.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_panel.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_pipe_crc.c (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_pipe_crc.h (84%)
rename drivers/gpu/drm/i915/{ => display}/intel_psr.c (97%)
rename drivers/gpu/drm/i915/{ => display}/intel_psr.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_quirks.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_quirks.h
rename drivers/gpu/drm/i915/{ => display}/intel_sdvo.c (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_sdvo.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_sdvo_regs.h (98%)
rename drivers/gpu/drm/i915/{ => display}/intel_sprite.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_sprite.h (89%)
rename drivers/gpu/drm/i915/{ => display}/intel_tv.c (99%)
rename drivers/gpu/drm/i915/{ => display}/intel_tv.h (100%)
rename drivers/gpu/drm/i915/{ => display}/intel_vbt_defs.h (71%)
rename drivers/gpu/drm/i915/{ => display}/intel_vdsc.c (99%)
create mode 100644 drivers/gpu/drm/i915/display/intel_vdsc.h
rename drivers/gpu/drm/i915/{ => display}/vlv_dsi.c (90%)
rename drivers/gpu/drm/i915/{ => display}/vlv_dsi_pll.c (98%)
create mode 100644 drivers/gpu/drm/i915/gem/Makefile
create mode 100644 drivers/gpu/drm/i915/gem/Makefile.header-test
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_busy.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_clflush.c (74%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_clflush.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_client_blt.h
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_context.c (63%)
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_context.h (69%)
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_context_types.h (75%)
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_dmabuf.c (83%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_domain.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_execbuffer.c (93%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_fence.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_internal.c (79%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_mman.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object_blt.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object_types.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_pages.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_phys.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_pm.h
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_shmem.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_shrinker.c (75%)
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_stolen.c (92%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_throttle.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_tiling.c (90%)
rename drivers/gpu/drm/i915/{ => gem}/i915_gem_userptr.c (94%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_wait.c
rename drivers/gpu/drm/i915/{ => gem}/i915_gemfs.c (51%)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gemfs.h
rename drivers/gpu/drm/i915/{ => gem}/selftests/huge_gem_object.c (70%)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
rename drivers/gpu/drm/i915/{ => gem}/selftests/huge_pages.c (93%)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
rename drivers/gpu/drm/i915/{ => gem}/selftests/i915_gem_coherency.c (83%)
rename drivers/gpu/drm/i915/{ => gem}/selftests/i915_gem_context.c (80%)
rename drivers/gpu/drm/i915/{ => gem}/selftests/i915_gem_dmabuf.c (85%)
rename drivers/gpu/drm/i915/{selftests/i915_gem_object.c =>
gem/selftests/i915_gem_mman.c} (67%)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
create mode 100644 drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
create mode 100644 drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
create mode 100644 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
create mode 100644 drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
rename drivers/gpu/drm/i915/{ => gem}/selftests/mock_context.c (54%)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/mock_context.h
rename drivers/gpu/drm/i915/{ => gem}/selftests/mock_dmabuf.c (73%)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
rename drivers/gpu/drm/i915/{ => gem}/selftests/mock_gem_object.h (65%)
create mode 100644 drivers/gpu/drm/i915/gt/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt}/intel_breadcrumbs.c (95%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_context.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_context.h
rename drivers/gpu/drm/i915/{ => gt}/intel_context_types.h (68%)
rename drivers/gpu/drm/i915/{intel_ringbuffer.h => gt/intel_engine.h} (90%)
rename drivers/gpu/drm/i915/{ => gt}/intel_engine_cs.c (82%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pm.h
rename drivers/gpu/drm/i915/{ => gt}/intel_engine_types.h (93%)
rename drivers/gpu/drm/i915/{ => gt}/intel_gpu_commands.h (99%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm.h
rename drivers/gpu/drm/i915/{ => gt}/intel_hangcheck.c (93%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc.c (74%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc.h (85%)
rename drivers/gpu/drm/i915/{ => gt}/intel_lrc_reg.h (97%)
rename drivers/gpu/drm/i915/{ => gt}/intel_mocs.c (98%)
rename drivers/gpu/drm/i915/{ => gt}/intel_mocs.h (97%)
rename drivers/gpu/drm/i915/{i915_reset.c => gt/intel_reset.c} (91%)
rename drivers/gpu/drm/i915/{i915_reset.h => gt/intel_reset.h} (91%)
rename drivers/gpu/drm/i915/{ => gt}/intel_ringbuffer.c (90%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sseu.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sseu.h
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds.c (81%)
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds.h (79%)
rename drivers/gpu/drm/i915/{ => gt}/intel_workarounds_types.h (88%)
rename drivers/gpu/drm/i915/{selftests => gt}/mock_engine.c (87%)
rename drivers/gpu/drm/i915/{selftests => gt}/mock_engine.h (95%)
rename drivers/gpu/drm/i915/{selftests/intel_engine_cs.c =>
gt/selftest_engine_cs.c} (100%)
rename drivers/gpu/drm/i915/{selftests/intel_hangcheck.c =>
gt/selftest_hangcheck.c} (88%)
rename drivers/gpu/drm/i915/{selftests/intel_lrc.c => gt/selftest_lrc.c} (68%)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_reset.c
rename drivers/gpu/drm/i915/{selftests/intel_workarounds.c =>
gt/selftest_workarounds.c} (62%)
create mode 100644 drivers/gpu/drm/i915/i915_debugfs.h
delete mode 100644 drivers/gpu/drm/i915/i915_gem_clflush.h
delete mode 100644 drivers/gpu/drm/i915/i915_gem_object.c
delete mode 100644 drivers/gpu/drm/i915/i915_gem_object.h
create mode 100644 drivers/gpu/drm/i915/i915_irq.h
create mode 100644 drivers/gpu/drm/i915/i915_scatterlist.c
create mode 100644 drivers/gpu/drm/i915/i915_scatterlist.h
delete mode 100644 drivers/gpu/drm/i915/intel_context.c
delete mode 100644 drivers/gpu/drm/i915/intel_context.h
create mode 100644 drivers/gpu/drm/i915/intel_runtime_pm.h
create mode 100644 drivers/gpu/drm/i915/intel_sideband.h
create mode 100644 drivers/gpu/drm/i915/intel_wakeref.c
create mode 100644 drivers/gpu/drm/i915/intel_wakeref.h
delete mode 100644 drivers/gpu/drm/i915/selftests/huge_gem_object.h
create mode 100644 drivers/gpu/drm/i915/selftests/igt_atomic.h
delete mode 100644 drivers/gpu/drm/i915/selftests/mock_context.h
delete mode 100644 drivers/gpu/drm/i915/selftests/mock_dmabuf.h
create mode 100644 drivers/gpu/drm/ingenic/Kconfig
create mode 100644 drivers/gpu/drm/ingenic/Makefile
create mode 100644 drivers/gpu/drm/ingenic/ingenic-drm.c
create mode 100644 drivers/gpu/drm/mcde/Kconfig
create mode 100644 drivers/gpu/drm/mcde/Makefile
create mode 100644 drivers/gpu/drm/mcde/mcde_display.c
create mode 100644 drivers/gpu/drm/mcde/mcde_display_regs.h
create mode 100644 drivers/gpu/drm/mcde/mcde_drm.h
create mode 100644 drivers/gpu/drm/mcde/mcde_drv.c
create mode 100644 drivers/gpu/drm/mcde/mcde_dsi.c
create mode 100644 drivers/gpu/drm/mcde/mcde_dsi_regs.h
create mode 100644 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c
create mode 100644 drivers/gpu/drm/panel/panel-samsung-s6e63m0.c
create mode 100644 drivers/gpu/drm/panfrost/panfrost_perfcnt.c
create mode 100644 drivers/gpu/drm/panfrost/panfrost_perfcnt.h
create mode 100644 drivers/gpu/drm/selftests/drm_cmdline_selftests.h
create mode 100644 drivers/gpu/drm/selftests/test-drm_cmdline_parser.c
delete mode 100644 drivers/gpu/drm/virtio/virtgpu_fb.c
create mode 100644 drivers/gpu/drm/virtio/virtgpu_trace.h
create mode 100644 drivers/gpu/drm/virtio/virtgpu_trace_points.c
create mode 100644 drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c
create mode 100644 drivers/gpu/ipu-v3/ipu-ic-csc.c
create mode 100644 include/drm/drm_gem_vram_helper.h
create mode 100644 include/drm/drm_self_refresh_helper.h
create mode 100644 include/drm/drm_vram_mm_helper.h
create mode 100644 mm/as_dirty_helpers.c