* configure.ac (sve2support, gcry_cv_gcc_inline_asm_aarch64_sve2)
(ENABLE_SVE2_SUPPORT): New.
* doc/gcrypt.texi: Add "sve2, sveaes, svepmull, svesha3, svesm4" to
ARM hardware features list.
* src/g10lib.h (HWF_ARM_SVE2, HWF_ARM_SVEAES, HWF_ARM_SVEPMULL)
(HWF_ARM_SVESHA3, HWF_ARM_SVESM4): New.
* src/hwf-arm.c (arm_features): Add
"sve2, sveaes, svepmull, svesha3, svesm4".
* src/hwfeatures.c (hwflist): Add
"arm-sve2, arm-sveaes, arm-svepmull, arm-svesha3, arm-svesm4".
--
Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
---
configure.ac | 54 ++++++++++++++++++++++++++++++++++++++++++++++++
doc/gcrypt.texi | 5 +++++
src/g10lib.h | 5 +++++
src/hwf-arm.c | 21 +++++++++++++++++++
src/hwfeatures.c | 5 +++++
5 files changed, 90 insertions(+)
diff --git a/configure.ac b/configure.ac
index b6c51ab9998d..31bcd77e3c75 100644
--- a/configure.ac
+++ b/configure.ac
@@ -706,6 +706,14 @@ AC_ARG_ENABLE(sve-support,
svesupport=$enableval,svesupport=yes)
AC_MSG_RESULT($svesupport)
+# Implementation of the --disable-sve2-support switch.
+AC_MSG_CHECKING([whether SVE2 support is requested])
+AC_ARG_ENABLE(sve2-support,
+ AS_HELP_STRING([--disable-sve2-support],
+ [Disable support for the ARMv9 SVE2 instructions]),
+ sve2support=$enableval,sve2support=yes)
+AC_MSG_RESULT($sve2support)
+
# Implementation of the --disable-ppc-crypto-support switch.
AC_MSG_CHECKING([whether PPC crypto support is requested])
AC_ARG_ENABLE(ppc-crypto-support,
@@ -1330,6 +1338,7 @@ if test "$mpi_cpu_arch" != "arm" ; then
neonsupport="n/a"
armcryptosupport="n/a"
svesupport="n/a"
+ sve2support="n/a"
fi
fi
@@ -2012,6 +2021,39 @@ if test "$gcry_cv_gcc_inline_asm_aarch64_sve" = "yes" ; then
fi
+#
+# Check whether GCC inline assembler supports AArch64 SVE2 instructions
+#
+AC_CACHE_CHECK([whether GCC inline assembler supports AArch64 SVE2 instructions],
+ [gcry_cv_gcc_inline_asm_aarch64_sve2],
+ [.if test "$mpi_cpu_arch" != "aarch64" ||
+ test "$try_asm_modules" != "yes" ; then
+ gcry_cv_gcc_inline_asm_aarch64_sve2="n/a"
+ else
+ gcry_cv_gcc_inline_asm_aarch64_sve2=no
+ AC_LINK_IFELSE([.AC_LANG_PROGRAM(
+ [.[.__asm__(
+ ".cpu generic+simd+sve2\n\t"
+ ".text\n\t"
+ "testfn:\n\t"
+ ";\n\t"
+ "eor3 z0.d, z0.d, z1.d, z2.d;\n\t"
+ "ext z8.b, {z20.b, z21.b}, \#3;\n\t"
+ "adclt z0.d, z1.d, z2.d;\n\t"
+ "tbl z0.b, {z8.b, z9.b}, z1.b;\n\t"
+ "addhnb z16.s, z17.d, z18.d;\n\t"
+ "mov z0.s, p0/z, \#55;\n\t"
+ "ld1b {z0.b}, p0/z, [x1];\n\t"
+ );
+ ]], [ testfn(); ])],
+ [gcry_cv_gcc_inline_asm_aarch64_sve2=yes])
+ fi])
+if test "$gcry_cv_gcc_inline_asm_aarch64_sve2" = "yes" ; then
+ AC_DEFINE(HAVE_GCC_INLINE_ASM_AARCH64_SVE2,1,
+ [Defined if inline assembler supports AArch64 SVE2 instructions])
+fi
+
+
#
# Check whether PowerPC AltiVec/VSX intrinsics
#
@@ -2507,6 +2549,13 @@ if test x"$svesupport" = xyes ; then
fi
fi
fi
+if test x"$sve2support" = xyes ; then
+ if test "$gcry_cv_gcc_inline_asm_sve2" != "yes" ; then
+ if test "$gcry_cv_gcc_inline_asm_aarch64_sve2" != "yes" ; then
+ sve2support="no (unsupported by compiler)"
+ fi
+ fi
+fi
if test x"$aesnisupport" = xyes ; then
AC_DEFINE(ENABLE_AESNI_SUPPORT, 1,
@@ -2552,6 +2601,10 @@ if test x"$svesupport" = xyes ; then
AC_DEFINE(ENABLE_SVE_SUPPORT,1,
[Enable support for ARMv8 SVE instructions.])
fi
+if test x"$sve2support" = xyes ; then
+ AC_DEFINE(ENABLE_SVE2_SUPPORT,1,
+ [Enable support for ARMv9 SVE2 instructions.])
+fi
if test x"$ppccryptosupport" = xyes ; then
AC_DEFINE(ENABLE_PPC_CRYPTO_SUPPORT,1,
[Enable support for POWER 8 (PowerISA 2.07) crypto extension.])
@@ -3435,6 +3488,7 @@ GCRY_MSG_SHOW([Try using Intel GFNI: ],[$gfnisupport])
GCRY_MSG_SHOW([Try using ARM NEON: ],[$neonsupport])
GCRY_MSG_SHOW([Try using ARMv8 crypto: ],[$armcryptosupport])
GCRY_MSG_SHOW([Try using ARMv8 SVE: ],[$svesupport])
+GCRY_MSG_SHOW([Try using ARMv9 SVE2: ],[$sve2support])
GCRY_MSG_SHOW([Try using PPC crypto: ],[$ppccryptosupport])
GCRY_MSG_SHOW([],[])
diff --git a/doc/gcrypt.texi b/doc/gcrypt.texi
index 5e07926bdaf0..f2c1cc948d23 100644
--- a/doc/gcrypt.texi
+++ b/doc/gcrypt.texi
@@ -602,6 +602,11 @@ are
@item arm-sm4
@item arm-sha512
@item arm-sve
+@item arm-sve2
+@item arm-sveaes
+@item arm-svepmull
+@item arm-svesha3
+@item arm-svesm4
@item ppc-vcrypto
@item ppc-arch_3_00
@item ppc-arch_2_07
diff --git a/src/g10lib.h b/src/g10lib.h
index 91d53ff37d96..8ba0a5c2aa0f 100644
--- a/src/g10lib.h
+++ b/src/g10lib.h
@@ -252,6 +252,11 @@ char **_gcry_strtokenize (const char *string, const char *delim);
#define HWF_ARM_SM4 (1 << 7)
#define HWF_ARM_SHA512 (1 << 8)
#define HWF_ARM_SVE (1 << 9)
+#define HWF_ARM_SVE2 (1 << 10)
+#define HWF_ARM_SVEAES (1 << 11)
+#define HWF_ARM_SVEPMULL (1 << 12)
+#define HWF_ARM_SVESHA3 (1 << 13)
+#define HWF_ARM_SVESM4 (1 << 14)
#elif defined(HAVE_CPU_ARCH_PPC)
diff --git a/src/hwf-arm.c b/src/hwf-arm.c
index 0bc2713b677f..500cd97a7179 100644
--- a/src/hwf-arm.c
+++ b/src/hwf-arm.c
@@ -157,6 +157,22 @@ static const struct feature_map_s arm_features[] =
# define HWCAP_SVE (1 << 22)
#endif
+#ifndef HWCAP2_SVE2
+# define HWCAP2_SVE2 (1 << 1)
+#endif
+#ifndef HWCAP2_SVEAES
+# define HWCAP2_SVEAES (1 << 2)
+#endif
+#ifndef HWCAP2_SVEPMULL
+# define HWCAP2_SVEPMULL (1 << 3)
+#endif
+#ifndef HWCAP2_SVESHA3
+# define HWCAP2_SVESHA3 (1 << 5)
+#endif
+#ifndef HWCAP2_SVESM4
+# define HWCAP2_SVESM4 (1 << 6)
+#endif
+
static const struct feature_map_s arm_features[] =
{
#ifdef ENABLE_NEON_SUPPORT
@@ -174,6 +190,11 @@ static const struct feature_map_s arm_features[] =
#endif
#ifdef ENABLE_SVE_SUPPORT
{ HWCAP_SVE, 0, " sve", HWF_ARM_SVE },
+ { 0, HWCAP2_SVE2, " sve2", HWF_ARM_SVE2 },
+ { 0, HWCAP2_SVEAES, " sveaes", HWF_ARM_SVEAES },
+ { 0, HWCAP2_SVEPMULL, " svepmull", HWF_ARM_SVEPMULL },
+ { 0, HWCAP2_SVESHA3, " svesha3", HWF_ARM_SVESHA3 },
+ { 0, HWCAP2_SVESM4, " svesm4", HWF_ARM_SVESM4 },
#endif
};
diff --git a/src/hwfeatures.c b/src/hwfeatures.c
index dec5efd3c196..b11cadefa9ef 100644
--- a/src/hwfeatures.c
+++ b/src/hwfeatures.c
@@ -75,6 +75,11 @@ static struct
{ HWF_ARM_SM4, "arm-sm4" },
{ HWF_ARM_SHA512, "arm-sha512" },
{ HWF_ARM_SVE, "arm-sve" },
+ { HWF_ARM_SVE2, "arm-sve2" },
+ { HWF_ARM_SVEAES, "arm-sveaes" },
+ { HWF_ARM_SVEPMULL, "arm-svepmull" },
+ { HWF_ARM_SVESHA3, "arm-svesha3" },
+ { HWF_ARM_SVESM4, "arm-svesm4" },
#elif defined(HAVE_CPU_ARCH_PPC)
{ HWF_PPC_VCRYPTO, "ppc-vcrypto" },
{ HWF_PPC_ARCH_3_00, "ppc-arch_3_00" },
--
2.24.3 (Apple Git-128)
_______________________________________________
Gcrypt-devel mailing list
Gcrypt-devel@lists.gnupg.org
https://lists.gnupg.org/mailman/listinfo/gcrypt-devel
(ENABLE_SVE2_SUPPORT): New.
* doc/gcrypt.texi: Add "sve2, sveaes, svepmull, svesha3, svesm4" to
ARM hardware features list.
* src/g10lib.h (HWF_ARM_SVE2, HWF_ARM_SVEAES, HWF_ARM_SVEPMULL)
(HWF_ARM_SVESHA3, HWF_ARM_SVESM4): New.
* src/hwf-arm.c (arm_features): Add
"sve2, sveaes, svepmull, svesha3, svesm4".
* src/hwfeatures.c (hwflist): Add
"arm-sve2, arm-sveaes, arm-svepmull, arm-svesha3, arm-svesm4".
--
Signed-off-by: Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
---
configure.ac | 54 ++++++++++++++++++++++++++++++++++++++++++++++++
doc/gcrypt.texi | 5 +++++
src/g10lib.h | 5 +++++
src/hwf-arm.c | 21 +++++++++++++++++++
src/hwfeatures.c | 5 +++++
5 files changed, 90 insertions(+)
diff --git a/configure.ac b/configure.ac
index b6c51ab9998d..31bcd77e3c75 100644
--- a/configure.ac
+++ b/configure.ac
@@ -706,6 +706,14 @@ AC_ARG_ENABLE(sve-support,
svesupport=$enableval,svesupport=yes)
AC_MSG_RESULT($svesupport)
+# Implementation of the --disable-sve2-support switch.
+AC_MSG_CHECKING([whether SVE2 support is requested])
+AC_ARG_ENABLE(sve2-support,
+ AS_HELP_STRING([--disable-sve2-support],
+ [Disable support for the ARMv9 SVE2 instructions]),
+ sve2support=$enableval,sve2support=yes)
+AC_MSG_RESULT($sve2support)
+
# Implementation of the --disable-ppc-crypto-support switch.
AC_MSG_CHECKING([whether PPC crypto support is requested])
AC_ARG_ENABLE(ppc-crypto-support,
@@ -1330,6 +1338,7 @@ if test "$mpi_cpu_arch" != "arm" ; then
neonsupport="n/a"
armcryptosupport="n/a"
svesupport="n/a"
+ sve2support="n/a"
fi
fi
@@ -2012,6 +2021,39 @@ if test "$gcry_cv_gcc_inline_asm_aarch64_sve" = "yes" ; then
fi
+#
+# Check whether GCC inline assembler supports AArch64 SVE2 instructions
+#
+AC_CACHE_CHECK([whether GCC inline assembler supports AArch64 SVE2 instructions],
+ [gcry_cv_gcc_inline_asm_aarch64_sve2],
+ [.if test "$mpi_cpu_arch" != "aarch64" ||
+ test "$try_asm_modules" != "yes" ; then
+ gcry_cv_gcc_inline_asm_aarch64_sve2="n/a"
+ else
+ gcry_cv_gcc_inline_asm_aarch64_sve2=no
+ AC_LINK_IFELSE([.AC_LANG_PROGRAM(
+ [.[.__asm__(
+ ".cpu generic+simd+sve2\n\t"
+ ".text\n\t"
+ "testfn:\n\t"
+ ";\n\t"
+ "eor3 z0.d, z0.d, z1.d, z2.d;\n\t"
+ "ext z8.b, {z20.b, z21.b}, \#3;\n\t"
+ "adclt z0.d, z1.d, z2.d;\n\t"
+ "tbl z0.b, {z8.b, z9.b}, z1.b;\n\t"
+ "addhnb z16.s, z17.d, z18.d;\n\t"
+ "mov z0.s, p0/z, \#55;\n\t"
+ "ld1b {z0.b}, p0/z, [x1];\n\t"
+ );
+ ]], [ testfn(); ])],
+ [gcry_cv_gcc_inline_asm_aarch64_sve2=yes])
+ fi])
+if test "$gcry_cv_gcc_inline_asm_aarch64_sve2" = "yes" ; then
+ AC_DEFINE(HAVE_GCC_INLINE_ASM_AARCH64_SVE2,1,
+ [Defined if inline assembler supports AArch64 SVE2 instructions])
+fi
+
+
#
# Check whether PowerPC AltiVec/VSX intrinsics
#
@@ -2507,6 +2549,13 @@ if test x"$svesupport" = xyes ; then
fi
fi
fi
+if test x"$sve2support" = xyes ; then
+ if test "$gcry_cv_gcc_inline_asm_sve2" != "yes" ; then
+ if test "$gcry_cv_gcc_inline_asm_aarch64_sve2" != "yes" ; then
+ sve2support="no (unsupported by compiler)"
+ fi
+ fi
+fi
if test x"$aesnisupport" = xyes ; then
AC_DEFINE(ENABLE_AESNI_SUPPORT, 1,
@@ -2552,6 +2601,10 @@ if test x"$svesupport" = xyes ; then
AC_DEFINE(ENABLE_SVE_SUPPORT,1,
[Enable support for ARMv8 SVE instructions.])
fi
+if test x"$sve2support" = xyes ; then
+ AC_DEFINE(ENABLE_SVE2_SUPPORT,1,
+ [Enable support for ARMv9 SVE2 instructions.])
+fi
if test x"$ppccryptosupport" = xyes ; then
AC_DEFINE(ENABLE_PPC_CRYPTO_SUPPORT,1,
[Enable support for POWER 8 (PowerISA 2.07) crypto extension.])
@@ -3435,6 +3488,7 @@ GCRY_MSG_SHOW([Try using Intel GFNI: ],[$gfnisupport])
GCRY_MSG_SHOW([Try using ARM NEON: ],[$neonsupport])
GCRY_MSG_SHOW([Try using ARMv8 crypto: ],[$armcryptosupport])
GCRY_MSG_SHOW([Try using ARMv8 SVE: ],[$svesupport])
+GCRY_MSG_SHOW([Try using ARMv9 SVE2: ],[$sve2support])
GCRY_MSG_SHOW([Try using PPC crypto: ],[$ppccryptosupport])
GCRY_MSG_SHOW([],[])
diff --git a/doc/gcrypt.texi b/doc/gcrypt.texi
index 5e07926bdaf0..f2c1cc948d23 100644
--- a/doc/gcrypt.texi
+++ b/doc/gcrypt.texi
@@ -602,6 +602,11 @@ are
@item arm-sm4
@item arm-sha512
@item arm-sve
+@item arm-sve2
+@item arm-sveaes
+@item arm-svepmull
+@item arm-svesha3
+@item arm-svesm4
@item ppc-vcrypto
@item ppc-arch_3_00
@item ppc-arch_2_07
diff --git a/src/g10lib.h b/src/g10lib.h
index 91d53ff37d96..8ba0a5c2aa0f 100644
--- a/src/g10lib.h
+++ b/src/g10lib.h
@@ -252,6 +252,11 @@ char **_gcry_strtokenize (const char *string, const char *delim);
#define HWF_ARM_SM4 (1 << 7)
#define HWF_ARM_SHA512 (1 << 8)
#define HWF_ARM_SVE (1 << 9)
+#define HWF_ARM_SVE2 (1 << 10)
+#define HWF_ARM_SVEAES (1 << 11)
+#define HWF_ARM_SVEPMULL (1 << 12)
+#define HWF_ARM_SVESHA3 (1 << 13)
+#define HWF_ARM_SVESM4 (1 << 14)
#elif defined(HAVE_CPU_ARCH_PPC)
diff --git a/src/hwf-arm.c b/src/hwf-arm.c
index 0bc2713b677f..500cd97a7179 100644
--- a/src/hwf-arm.c
+++ b/src/hwf-arm.c
@@ -157,6 +157,22 @@ static const struct feature_map_s arm_features[] =
# define HWCAP_SVE (1 << 22)
#endif
+#ifndef HWCAP2_SVE2
+# define HWCAP2_SVE2 (1 << 1)
+#endif
+#ifndef HWCAP2_SVEAES
+# define HWCAP2_SVEAES (1 << 2)
+#endif
+#ifndef HWCAP2_SVEPMULL
+# define HWCAP2_SVEPMULL (1 << 3)
+#endif
+#ifndef HWCAP2_SVESHA3
+# define HWCAP2_SVESHA3 (1 << 5)
+#endif
+#ifndef HWCAP2_SVESM4
+# define HWCAP2_SVESM4 (1 << 6)
+#endif
+
static const struct feature_map_s arm_features[] =
{
#ifdef ENABLE_NEON_SUPPORT
@@ -174,6 +190,11 @@ static const struct feature_map_s arm_features[] =
#endif
#ifdef ENABLE_SVE_SUPPORT
{ HWCAP_SVE, 0, " sve", HWF_ARM_SVE },
+ { 0, HWCAP2_SVE2, " sve2", HWF_ARM_SVE2 },
+ { 0, HWCAP2_SVEAES, " sveaes", HWF_ARM_SVEAES },
+ { 0, HWCAP2_SVEPMULL, " svepmull", HWF_ARM_SVEPMULL },
+ { 0, HWCAP2_SVESHA3, " svesha3", HWF_ARM_SVESHA3 },
+ { 0, HWCAP2_SVESM4, " svesm4", HWF_ARM_SVESM4 },
#endif
};
diff --git a/src/hwfeatures.c b/src/hwfeatures.c
index dec5efd3c196..b11cadefa9ef 100644
--- a/src/hwfeatures.c
+++ b/src/hwfeatures.c
@@ -75,6 +75,11 @@ static struct
{ HWF_ARM_SM4, "arm-sm4" },
{ HWF_ARM_SHA512, "arm-sha512" },
{ HWF_ARM_SVE, "arm-sve" },
+ { HWF_ARM_SVE2, "arm-sve2" },
+ { HWF_ARM_SVEAES, "arm-sveaes" },
+ { HWF_ARM_SVEPMULL, "arm-svepmull" },
+ { HWF_ARM_SVESHA3, "arm-svesha3" },
+ { HWF_ARM_SVESM4, "arm-svesm4" },
#elif defined(HAVE_CPU_ARCH_PPC)
{ HWF_PPC_VCRYPTO, "ppc-vcrypto" },
{ HWF_PPC_ARCH_3_00, "ppc-arch_3_00" },
--
2.24.3 (Apple Git-128)
_______________________________________________
Gcrypt-devel mailing list
Gcrypt-devel@lists.gnupg.org
https://lists.gnupg.org/mailman/listinfo/gcrypt-devel