Mailing List Archive

For the sake of completion and archival it appears that this message can occur when the line card is faulty.

-----Original Message-----
From: cisco-nsp <cisco-nsp-bounces@puck.nether.net> On Behalf Of Drew Weaver
Sent: Tuesday, December 7, 2021 1:56 PM
To: cisco-nsp@puck.nether.net
Subject: [c-nsp] IOS XR 'STARKAD Mother Board FPGA' detected clock reference failure / DPLL unlock indicator on 'ZARLINK Bus'. Instance reporting the problem is 1

Hey,

I have an ASR9k with a 4x10GE card in a MOD80-TR. All four of the ports are in a bundle-ether.

About a week ago we began having flaps on all four of the ports in the bundle.

We just yesterday started seeing messages like this:

IOS XR 'STARKAD Mother Board FPGA' detected clock reference failure / DPLL unlock indicator on 'ZARLINK Bus'. Instance reporting the problem is 1

I looked up the issue, it shouldn't apply due to the software version and we don't use clock synchronization.

What I am wondering is if anyone has seen this particular error message before outside of Cisco's description of what causes it?

Just wondering.
-Drew

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